4-12

DIGITAL INPUTS

CE1, CE2

Note 4

-

-

V

Phase, CLK

Note 4

-

-

V

CE1, CE2

Note 4

--

V

Phase, CLK

Note 4

--

V

Note 3

-

±0.2

±5

µA

-3-

pF

DIGITAL OUTPUTS

Output Low (Sink) Current

4

10

-

mA

Output High (Source) Current

-4

-6

-

mA

-

±0.2

±5

µA

-4-

pF

TIMING CHARACTERISTICS

Auto Balance Time (

33

-

∞

ns

Sample Time (

Note 4

25

-

500

ns

Aperture Delay

-15-

ns

Aperture Jitter

-

100

-

ps

Note 4

-

50

65

ns

Note 4

25

40

-

ns

-18-

ns

-18-

ns

POWER SUPPLY CHARACTERISTICS

Continuous Conversion (Note 4)

-

30

60

mA

Auto Balance (

-

30

60

mA

NOTES:

The -3dB bandwidth for frequency response purposes is greater than 30MHz.

3. The clock input is a CMOS inverter with a 50k

4. Parameter not tested, but guaranteed by design or characterization.

Timing Waveforms

FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM

Electrical Specifications

All Reference Points Adjusted, Unless Otherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

COMPARATOR DATA IS LATCHED

DECODED DATA IS SHIFTED

TO OUTPUT REGISTERS

SAMPLE

N

CLOCK (PIN 18)

IF PHASE (PIN 19)

IS LOW

CLOCK IF

PHASE IS HIGH

AUTO

BALANCE

SAMPLE

N + 1

DATA

N - 2

AUTO

BALANCE

SAMPLE

N + 2

DATA

N - 1

DATA

N

CA3318