7-918

CD4048BMS

FIGURE 3. ACTUAL CIRCUIT LOGIC CONFIGURATIONS

Applications of Expand Input

FIGURE 4. 12 INPUT OR/AND GATE

FIGURE 5. 16 INPUT NOR GATE

IMPLEMETATION OF EXPAND INPUT FOR 9 OR MORE INPUTS

OUTPUT FUNCTION

FUNCTION NEEDED AT EXPAND INPUT

OUTPUT BOOLEAN EXPRESSION

NOR

OR

J=(A+B+C+D+E+F+G+H)+(EXP)

OR

OR

J=(A+B+C+D+E+F+G+H)+(EXP)

AND

NAND

J=(ABCDEFGH)

•(EXP)

NAND

NAND

J=(ABCDEFGH)

•(EXP)

OR/AND

NOR

J=(A+B+C+D)

•(E+F+G+H)•(EXP)

OR/NAND

NOR

J=(A+B+C+D)

•(E+F+G+H)•(EXP)

AND/NOR

AND

J=(ABCD)+(EFGH)+(EXP)

AND/OR

AND

J=(ABCD)+(EFGH)+(EXP)

NOTES: 1. (EXP) designates the EXPAND function (i.e., X1 + X2 + . . .XN).

2. Refer to FUNCTION TRUTH TABLE for connection of unused inputs.

11

12

13

14

3

4

5

6

15

Ka - Kb - Kc

0 - 0 - 0

NOR

NAND

1 - 0 - 1

1 - 0 - 0

1 - 1 - 0

0 - 1 - 1

0 - 0 - 1

0 - 1 - 0

1 - 1 - 1

AND

AND/NOR

OR/NAND

OR

AND/OR

OR/AND

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

J (OUTPUT)

Kd

H

G

F

E

VSS

Kb

VDD

A

B

C

D

Ka

Kc

VSS

X1

X2

X3

X4

VDD

1/2 CD4002A

VDD

12 - INPUT OR/AND GATE

J = (A+B+C+D)

(E+F+G+H)

(X1+X2+X3+X4)

..

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

OUTPUT

Kd

H1

G1

F1

E1

VSS

Kb

VDD

A1

B1

C1

D1

Ka

Kc

VDD

VSS

VSS

VDD

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

J(OUTPUT)

Kd

H2

G2

F2

E2

VSS

Kb

VDD

A2

B2

C2

D2

Ka

Kc

VSS

EXP

VDD

OR FUNCTION

16 - INPUT NOR GATE

J = A1 +B1 +C1 +D1 +E1 +F1 +G1 +H1 +A2 +B2 +C2 +D2 +E2 +F2 +G2 +H2