HC5515IP datasheet(12/17 Pages) INTERSIL

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Longitudinal Impedance

The feedback loop described in Figure 19(A, B) realizes the

desired longitudinal impedances from tip to ground and from

ring to ground. Nominal longitudinal impedance is resistive

and in the order of 22

Ω.

In the presence of longitudinal currents this circuit

attenuates the voltages that would otherwise appear at the

tip and ring terminals, to levels well within the common mode

range of the SLIC. In fact, longitudinal currents may exceed

the programmed DC loop current without disturbing the

SLIC’s VF transmission capabilities.

The function of this circuit is to maintain the tip and ring

voltages symmetrically around VBAT/2, in the presence of

longitudinal currents. The differential transconductance

ampliﬁers GT and GR accomplish this by sourcing or sinking

the required current to maintain VC at VBAT/2.

When a longitudinal current is injected onto the tip and ring

inputs, the voltage at VC moves from it’s equilibrium value

VBAT/2. When VC changes by the amount DVC, this change

appears between the input terminals of the differential

transconductance ampliﬁers GT and GR. The output of GT

and GR are the differential currents DI1 and DI2, which in

turn feed the differential inputs of current sources IT and IR

respectively. IT and IR have current gains of 250 single

ended and 500 differentially, thus leading to a change in IT

and IR that is equal to 500(DI) and 500(DI2).

The circuit shown in Figure 19(B) illustrates the tip side of

the longitudinal network. The advantages of a differential

input current source are: improved noise since the noise due

to current source 2IO is now correlated, power savings due

to differential current gain and minimized offset error at the

Operational Ampliﬁer inputs via the two 5k

Ω resistors.

Digital Logic Inputs

Table 1 is the logic truth table for the TTL compatible logic

input pins. The HC5515 has an enable input pin (E0) and

two control inputs pins (C1, C2).

The enable pin E0 is used to enable or disable the DET

output pin. The DET pin is enabled if E0 is at a logic level 0

and disabled if E0 is at a logic level 1.

A combination of the control pins C1 and C2 is used to

select 1 of the 4 possible operating states. A description of

each operating state and the control logic follow:

Open Circuit State (C1 = 0, C2 = 0)

In this state the SLIC is effectively off. All detectors and

both the tip and ring line drive amplifiers are powered

down, presenting a high impedance to the line. Power

dissipation is at a minimum.

Active State (C1 = 0, C2 = 1)

The tip output is capable of sourcing loop current and for

open circuit conditions is about -4V from ground. The ring

output is capable of sinking loop current and for open circuit

conditions is about VBAT +4V. VF signal transmission is

normal. The loop current detector is active, E0 determines if

the detector is gated to the DET output.

TIP

RING

HC5515

RRT

VBAT

ERG

RING TRIP

COMPARATOR

DET

CRT

RINGRLY

RING

RELAY

FIGURE 18. RING TRIP CIRCUIT FOR BATTERY BACKED

RINGING

TIP

RING

VBAT/2

∆I1

∆I2

RLARGE

∆VT

ILONG

HC5515

ILONG

∆VR

VBAT/2

RLARGE

TIP

RING

Ω

2I0

∆I1

TIP CURRENT SOURCE

WITH DIFFERENTIAL INPUTS

TIP DIFFERENTIAL

TRANSCONDUCTANCE

AMPLIFIER

FIGURE 19A.

FIGURE 19B.

FIGURE 19. LONGITUDINAL IMPEDANCE NETWORK

HC5515

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