AD9806 datasheet(4/12 Pages) AD

4 / 12 page

REV. 0

–4–

AD9806–SPECIFICATIONS

AUX-MODE SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

POWER CONSUMPTION

Normal (D-Reg 00)

High-Speed (D-Reg 01)

MAXIMUM CLOCK RATE

Normal (D-Reg 00)

MHz

High-Speed (D-Reg 01)

28.6

MHz

PGA (Gain Selected through Serial Interface F-Reg)

Max Input Range

700

mV p-p

Max Output Range

1000

mV p-p

Gain Control Resolution

Bits

Gain Range

Min Gain (Code 128)

–2

Max Gain (Code 255)

ACTIVE CLAMP

Clamp Level (Selected through Serial Interface E-Reg)

CLP0 (E-Reg 00)

LSB

CLP1 (E-Reg 01)

LSB

CLP2 (E-Reg 10)

LSB

CLP3 (E-Reg 11)

LSB

TIMING SPECIFICATIONS

Pipeline Delay

Cycles

Internal Clock Delay (tID)

Output Delay (tOD)

14.5

Output Hold Time (tHOLD)7

NOTES

120 pF loading; timing shown in Figure 2.

Specifications subject to change without notice.

AUXMID-MODE SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

POWER CONSUMPTION

MAXIMUM CLOCK RATE

MHz

PGA (Gain Selected through Serial Interface F-Reg)

Max Input Range

700

mV p-p

Max Output Range

1000

mV p-p

Gain Control Resolution

Bits

Gain Range (See Figure 5b for Gain Curve)

Min Gain (Code 512)

–4

Max Gain (Code 1023)

MIDSCALE OFFSET LEVEL (AT MAX PGA GAIN)

462

512

562

LSB

TIMING SPECIFICATIONS1

Pipeline Delay

Cycles

Internal Clock Delay (tID)

Output Delay (tOD)

14.5

Output Hold Time (tHOLD)7

NOTES

120 pF loading; timing shown in Figure 2.

Specifications subject to change without notice.

(TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.)

AD9806 Datasheet(PDF) 4 Page - Analog Devices

AD9806 Datasheet(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Link URL