AD9835 datasheet(21/28 Pages) AD

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Data Sheet

AD9835

Rev. A | Page 21 of 28

AD9835-TO-68HC11/68L11 INTERFACE

Figure 27 shows the serial interface between the AD9835 and

the 68HC11/68L11 microcontroller. The microcontroller is

configured as the master by setting bit MSTR in the SPCR to 1

and, this provides a serial clock on SCK while the MOSI output

drives the serial data line SDATA. Since the microcontroller

does not have a dedicated frame sync pin, the FSYNC signal is

derived from a port line (PC7). The setup conditions for correct

operation of the interface are as follows: the SCK idles high

between write operations (CPOL = 0), data is valid on the SCK

falling edge (CPHA = 1). When data is being transmitted to the

AD9835, the FSYNC line is taken low (PC7). Serial data from

the 68HC11/68L11 is transmitted in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. In order to load data into the AD9835, PC7

is held low after the first eight bits are transferred and a second

serial write operation is performed to the AD9835. Only after

the second eight bits have been transferred should FSYNC be

taken high again.

AD9835*

FSYNC

SDATA

SCLK

68HC11/68L11*

PC7

MOSI

SCK

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 27. 68HC11/68L11-to-AD9835 Interface

AD9835-TO-80C51/80L51 INTERFACE

Figure 26 shows the serial interface between the AD9835 and

the 80C51/80L51 microcontroller. The microcontroller is

operated in Mode 0 so that TXD of the 80C51/80L51 drives

SCLK of the AD9835 while RXD drives the serial data line

SDATA. The FSYNC signal is again derived from a bit

programmable pin on the port (P3.3 being used in the

diagram). When data is to be transmitted to the AAD9835,

P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit

bytes thus, only eight falling SCLK edges occur in each cycle.

To load the remaining eight bits to the AD9835, P3.3 is held

low after the first eight bits have been transmitted and a second

write operation is initiated to transmit the second byte of data.

P3.3 is taken high following the completion of the second write

operation. SCLK should idle high between the two write

operations. The 80C51/ 80L51 outputs the serial data in a

format which has the LSB first. The AD9835 accepts the MSB

first (the 4 MSBs being the control information, the next 4 bits

being the address while the 8 LSBs contain the data when

writing to a destination register). Therefore, the transmit

routine of the 80C51/80L51 must take this into account and

rearrange the bits so that the MSB is output first.

AD9835*

FSYNC

SDATA

SCLK

80C51/80L51*

P3.3

RxD

TxD

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 28. 80C51/80L51 to AD9835 Interface

AD9835-TO-DSP56002 INTERFACE

Figure 29 shows the interface between the AD9835 and the

DSP56002. The DSP56002 is configured for normal mode

asynchronous operation with a gated internal clock (SYN = 0,

GCK = 1, SCKD = 1). The frame sync pin is generated internally

(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0)

and the frame sync signal will frame the 16 bits (FSL = 0).

The frame sync signal is available on pin SC2 but, it needs to be

inverted before being applied to the AD9835. The interface to

the DSP56000/DSP56001 is similar to that of the DSP56002.

AD9835*

FSYNC

SDATA

SCLK

DSP56002*

SC2

STD

SCK

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 29. AD9835-to-DSP56002 Interface

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