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UPC1862GS Datasheet(PDF) 28 Page - NEC

Part # UPC1862GS
Description  BURST LOCK CLOCK GENERATOR
PDF  32 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPC1862GS Datasheet(HTML) 28 Page - NEC

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µPC1862
Care Point for Planning of Application Circuit
1.
Processing of VCC pin
Please isolate Chroma. VCC from Sync. VCC as follows. If you have external processing block of digital signal, don’t
directly supply of the block’s VDD.
2.
Application of no using Chroma pin
If you don’t use Chroma pin but use Sync pin on
µPC1862, you process pin 1 to pin 18 as follows.
3.
Application of no using Sync pin
If you don’t use Sync pin but use Chroma pin on
µPC1862, you process pin 19 to pin 36 as follows. In this case, you
need to input a pin 24 with burst gate pulse from external.
In this application, you can’t use output of pin 20 to pin 23.
Processing IC of
digital signal, etc
VDD
SGND
5 V
SVCC
GND
CGND
CVCC1
CVCC2
CVCC3
0.01 F
47 F
0.01 F
0.01 F 47 F
Sync (Pin 19 to pin 36)
PC1862
Chroma (Pin 1 to pin 18)
30
25
14
10
215
µµ
µ
µµ
µ
5 V
TINT
CVCC1
CVCC3
CVCC2
0.01
F
47 F
0.01 F
SCO
CIN
CKO
ACCF
CKF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
COUT APCF CGND SCOF1 SCOF2 SCOF3
VCOO DIVS ESCI
PC1862
µ
µ
µ
µ
5 V
HSOF2
SVCC
3.3 k
Ω
3.3 k
Ω
5 V
0 V
2.2 k
Ω
Open
(Don’t use)
Burst Gate Input
Video signal
input
Comp Sync Output
Open
SSI
CSO VSSI HDF
36
35
33
34
32
31
30
29
28
27
26
25
24
23
22
21
20
19
HDO
SGND HSOF1
HKO
HSOF3 AFCF
BGPE NHSO CPO
FIO
VSO
N/P
PC1862
µ



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