AD9877 datasheet(19/36 Pages) AD

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AD9877

Rev. B | Page 19 of 36

Bits 0–4: OSCIN Multiplier

This register field is used to program the on-chip multiplier

(PLL) that generates the chip’s high frequency system clock fSYSCLK.

To multiply the external crystal clock fOSCIN by 16 decimals, for

example, program Register 0x00, Bits 4:0 as 0x10. The default

value of M is 0x08. Valid entries range from M = 1 to 31. When

M equals 1, the PLL is disabled. All internal clocks are derived

directly from OSCIN.

The PLL requires 200 MCLK cycles to regain frequency lock

after a change in M, the clock multiplier value. After the

recapture time of the PLL, the frequency of fSYSCLK is stable.

For timing integrity, certain restrictions on the values of M and

N apply when both AD9877 transmit and receive paths are

used. The supported modes are shown in Table 5.

Table 5. ADC Clock Select

ADC Clock Select

1, fOSCIN

0, fMCLK (PLL derived)

Bit 5: RESET

Writing a 1 to this bit resets the registers to their default values

and restarts the chip. The RESET bit always reads back 0. The

bits in Register 0x00 are not affected by this software reset. A

low level at the RESET pin, however, would force all registers,

including all bits in Register 0x00, to their default state.

Bit 6: LSB First

Active high indicates SPI serial port access of instruction byte

and data registers are least significant bit (LSB) first. Default low

indicates most significant bit (MSB) first format.

Bit 7: SDIO Bidirectional

Active high configures the serial port as a three-signal port with

the SDIO pin used as a bidirectional input/output pin. Default

low indicates the serial port uses four signals with SDIO con-

figured as an input and SDO configured as an output.

Bits 0–5: MCLK Divider

This register determines the output clock on the REFCLK pin.

At default zero (R = 0), REFCLK provides a buffered version of

the OSCIN clock signal for other chips.

The register can also be used to divide the chip’s master clock,

fMCLK, by R, where R is an integer between 2 and 63. The

generated reference clock on the REFCLK pin can be used for

external frequency controlled devices.

Bit 6: SYSCLK Divider

The OSCIN multiplier output clock, fSYSCLK, can be divided by 4

or 3 to generate the chip’s master clock. Active high indicates a

divide ratio of N = 3. Default low configures a divide ratio of

N = 4.

Bit 7: PLL Lock Detect

When this bit is set low, the REFCLK pin functions in its default

mode and provides an output clock with frequency fMCLK/R, as

described previously.

If this bit is set to 1, the REFCLK pin is configured to indicate

whether the PLL is locked to fOSCIN. In this mode, the REFCLK

pin should be low-pass filtered with an RC filter of 1.0 kΩ and

0.1 μF. A high output on REFCLK indicates the PLL has

achieved lock with fOSCIN.

Sections of the chip that are not used can be powered down

when the corresponding bits are set high. This register has a

default value of 0x00, with all sections active.

Bit 0: Power-Down 8-Bit ADC

Active high powers down the 8-bit ADC.

Bit 3: Power-Down 12-Bit ADC Reference

Active high powers down the 12-bit ADC reference.

Bit 4: Power-Down 12-Bit ADC

Active high powers down the 12-bit ADC.

Bit 5: Power-Down Digital Tx

Active high powers down the digital transmit section of the

chip, similar to the function of the PWRDN pin.

Bit 6: Power-Down DAC Tx

Active high powers down the DAC.

Bit 7: Power-Down PLL

Active high powers down the OSCIN multiplier.

The Σ-Δ control words are 12 bits wide and split into MSB Bits

[11:4] and LSB Bits [3:0]. Changes to the Σ-Δ control words

take effect immediately for every MSB or LSB register write.

Σ-Δ output control words have a default value of 0. The control

words are in straight binary format, with 0x000 corresponding

to the bottom of the scale and 0xFFF corresponding to the top

of the scale (see Figure 19 for details).

If flag enable (Bit 0 of Register 0x03 or 0x05) is set high, the

SDELTA pins maintains a fixed logic level determined directly

by the MSB of the Σ-Δ control word.

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