AD9991_15 datasheet(41/60 Pages) AD

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AD9991

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Table XIX. Timing Core Register Map

Data Bit Default

Address Content

Value

[0]

CLIDIVIDE

Divide CLI Input Clock by 2. 1 = Divide by 2.

[12:0]

01001

H1CONTROL

H1 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).

H1 Positive Edge Location [6:1]. H1 Negative Edge Location [12:7].

[12:0]

01001

H3CONTROL

H3 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).

H3 Positive Edge Location [6:1]. H3 Negative Edge Location [12:7].

[12:0]

00801

RGCONTROL

RG Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).

RG Positive Edge Location [6:1]. RG Negative Edge Location [12:7].

[1:0]

HBLKRETIME

Retime HBLK to Internal H1/H3 Clocks. H1 Retime [0]. H3 Retime [1].

Preferred setting is 1 for each bit. Setting each bit to 1 will add one cycle delay

to HBLK toggle positions.

[14:0]

1249

DRVCONTROL

Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and

RG [14:12]. Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA,

3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.

[11:0]

00024

SAMPCONTROL

SHP/SHD Sample Control: SHP Sampling Location [5:0].

SHD Sampling Location [11:6].

[8:0]

100

DOUTCONTROL

DOUT Phase Control [5:0]. DCLK Mode [6]. DOUTDELAY [8:7].

Table XX. CLPOB Masking Register Map

Data Bit Default

Address Content

Value

[23:0]

FFFFFF CLPMASK01

CLPOB Line Masking. Line #0 [11:0]. Line #1 [23:0].

[23:0]

FFFFFF CLPMASK23

CLPOB Line Masking. Line #2 [11:0]. Line #3 [23:0].

[11:0]

FFFFFF CLPMASK4

CLPOB Line Masking. Line #4 [11:0].

Table XXI. SG Pattern Register Map

Data Bit Default

Address Content

Value

[3:0]

SGPOL

Start Polarity for SG Patterns. Pattern #0 [0]. Pattern #1 [1].

Pattern #2 [2]. Pattern #3 [3].

[23:0]

FFFFFF SGTOG12_0

Pattern #0. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].

[23:0]

FFFFFF SGTOG12_1

Pattern #1. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].

[23:0]

FFFFFF SGTOG12_2

Pattern #2. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].

[23:0]

FFFFFF SGTOG12_3

Pattern #3. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].

Table XXII. Shutter Control Register Map

Data Bit Default

Address Content

Value

[4:0]

TRIGGER

Trigger for VSUB [0], MSHUT [1], STROBE [2], Exposure [3], and

Readout [4]. Note that to trigger the Readout to automatically occur after the

Exposure period, both Exposure and Readout should be triggered together.

[2:0]

READOUT

Number of Fields to Suppress the SUBCK Pulses after the VSG Line.

[11:0]

EXPOSURE

Number of Fields to Suppress the SUBCK and VSG Pulses.

[12]

VDHDOFF

Set = 1 to Disable the VD/HD Outputs during exposure (when >1 ﬁeld).

[11:0]

SUBCKSUPPRESS

Number of SUBCK Pulses to Suppress after VSG Line.

[23:12]

SUBCKNUM

Number of SUBCK Pulses per Field.

[0]

SUBCKPOL

SUBCK Pulse Start Polarity.

[23:0]

FFFFFF SUBCK1TOG

First SUBCK Pulse. Toggle Position 1 [11:0]. Toggle Position 2 [23:0].

[23:0]

FFFFFF SUBCK2TOG

Second SUBCK Pulse. Toggle Position 1 [11:0]. Toggle Position 2 [23:0].

REV. 0

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