AD9991_15 datasheet(22/60 Pages) AD

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AD9991

–22–

The example shown in Figure 22 illustrates this operation. The

ﬁrst toggle position is 2, and the second toggle position is 9. In

non-Multiplier mode, this would cause the V-sequence to toggle

at pixel 2 and then pixel 9 within a single HD line. However,

toggle positions are now multiplied by the VTPLEN = 4, so the

ﬁrst toggle occurs at pixel count 8, and the second toggle occurs

at pixel count 36. Sweep mode has also been enabled to allow the

toggle positions to cross the HD line boundaries.

Vertical Sensor Gate (Shift Gate) Patterns

In an Interline CCD, the vertical sensor gates (VSG) are used

to transfer the pixel charges from the light-sensitive image area

into light-shielded vertical registers. From the light-shield verti-

cal registers, the image is then read out line-by-line by using the

vertical transfer pulses V1–V6 in conjunction with the high speed

horizontal clocks.

Table IX contains the summary of the VSG pattern registers. The

AD9991 has ﬁve VSG outputs, VSG1–VSG5. Each of the out-

puts can be assigned to one of four programmed patterns by using

the SGPATSEL registers. Each pattern is generated in a similar

manner as the V-pattern groups, with a programmable start polar-

ity (SGPOL), ﬁrst toggle position (SGTOG1), and second toggle

position (SGTOG2). The active line where the VSG1–VSG5

pulses occur is programmable using the SGLINE1 and SGLINE2

registers. Additionally, any of the VSG1–VSG5 pulses may be

individually disabled by using the SGMASK register. The individ-

ual masking allows all of the SG patterns to be preprogrammed,

and the appropriate pulses for the different ﬁelds can be separately

enabled. For maximum ﬂexibility, the SGPATSEL, SGMASK,

and SGLINE registers are separately programmable for each ﬁeld.

More detail is given in the Complete Field section.

V1–V6

VPATLEN

MULTIPLIER MODE V-PATTERN GROUP PROPERTIES:

1. START POLARITY (ABOVE: STARTPOL = 0)

2. FIRST, SECOND, AND THIRD TOGGLE POSITIONS (ABOVE: VTOG1 = 2, VTOG2 = 9)

3. LENGTH OF VPAT COUNTER (ABOVE: VPATLEN = 4). THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.

4. TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTOG

VPATLEN)

5. IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE

123412341234123412341234

START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS

PIXEL

NUMBER

234

5678

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Figure 22. Example of Multiplier Region for Wide Vertical Pulse Timing

Table IX. VSG Pattern Registers (also see Field Registers in Table VII)

Length

Range

Description

SGPOL

High/Low

Sensor Gate Starting Polarity for SG Pattern 0–3

SGTOG1

12b

0–4095 Pixel Location

First Toggle Position for SG Pattern 0–3

SGTOG2

12b

0–4095 Pixel Location

Second Toggle Position for SG Pattern 0–3

PROGRAMMABLE SETTINGS FOR EACH PATTERN:

1. START POLARITY OF PULSE

2. FIRST TOGGLE POSITION

3. SECOND TOGGLE POSITION

4. ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN)

VSG PATTERNS

Figure 23. Vertical Sensor Gate Pulse Placement

REV. 0

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