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HIP7020AP Datasheet(PDF) 9 Page - Intersil Corporation |
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HIP7020AP Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 11 page ![]() 9 TRANSMIT (TX) The TRANSMIT pin will accept standard CMOS/TTL logic level input data. Logic level data is input at the TRANSMIT (TX) pin in a serial format, such as provided by a Intersil HIP7030A2 J1850 Controller, and is output on the J1850 Bus at the BUS OUT pin. The TX input has an active pull down current sink to insure that a logic level low will be main- tained when no signal drive is present. RECEIVE (RX) The RX pin is the output for J1850 Bus data and interfaces to an open collector transistor output driver. The RX digital data output is inverted from the analog bus data input at the BUSIN pin. The data from the RX pin is output to a Intersil HIP7010 Byte Level I/O or a HIP7030A2 J1850 Microcontrol- ler IC where the 10.4 Kbps VPWM messages from the J1850 network are decoded. GROUND This is the HIP7020 Bus Transceiver IC ground reference for all the signals which interface to the control logic and the J1850 bus. It is also the ground return path for the BATTERY power supply to IC. R/F TIME The R/F (Rise/Fall) Time pin connects the external resistor, RS, from the wave shaped voltage reference to ground. The Rise and Fall Time is controlled by the transition slope of the signal waveform. The resistor, RS, sets an internal current reference to control the rise and fall slope. As previously noted, the resis- tor, RS, should be located as close as possible to the IC to min- imize noise coupling to the R/F pin. Also, the ground connection of RS must be made directly to the GND pin of the IC with no other current flowing in the connecting line. BUS IN The BUS IN pin is the receive input of the SAE J1850 Bus signal. It receives the 10.4kHz VPWM (Variable pulse width modulated) data from the single wire analog serial bus through an external Resistor, RF. BUS OUT The BUS OUT pin transmits the SAE J1850 10.4kHz VPWM (Variable Pulse Width Modulated) data to the serial bus. Data is transmitted to the serial J1850 bus with the same polarity as the TX input signal. LB EN The LB EN Loop-Back Enable pin controls the Diagnostic Loop-Back Mode Switch function. A logic low on the LB EN pin connects the output of the Wave Shaped Voltage Refer- ence to the Bus Receiver and Voltage Comparator while dis- connecting the filtered input of J1850 Bus. This feature provides the means to trouble shoot system problems. HIP7020 |
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