4-10

The digital block diagram shows the programming flow of the

chip. An eight bit word is received at the MISO port. Data is

shifted in by the SCK clock when the chip is enabled by the

CS pin. The word is decoded by the address decoding

circuit, and the information is directed to one of 5 registers.

These registers control:

1. Reference knock filter frequency.

2. Knock filter frequency.

3. Balance control or attenuation of one channel with

respect to the other.

4. Integration time constant of the sum of the two channels.

5. One of 3 functions.

a) test conditions of the part.

b) channel select to one of two sensors.

c) channel to be attenuated.

A crystal oscillator circuit is provided. The chip requires a 4MHz

crystal to be connected across OSCIN and OSCOUT pins.

In the test mode, use the digital multiplexer to output one of

the following signals:

1. Contents of one of the five registers in the chip.

2. Inverted signal of the MOSI pin.

3. Voltage of an internal comparator used to rectify the

analog signal.

Upon power up, chip requires that the INT/HOLD pin is

toggled. If this is not done then it is important to note, that

only the first result and SPI data bytes sent after power up

will not be valid. Any subsequent chip operation will then be

performed correctly.

REFERENCE FILTER

KNOCK FILTER

BALANCE CONTROL

INTEGRATOR TIME CONSTANT

TEST/ CHANNEL SELECT ATTENUATE

OSCILLATOR

CIRCUIT

ADDRESS DECODER

MOSI

SCK

CS

MOSI

TEST

COMPARATOR OUT

MISO

OSCOUT

OSCIN

(FROM RECTIFIER PHASE

DETECTOR)

FIGURE 5. DIGITAL BLOCK DIAGRAM

TABLE 3. SPI TIMING REQUIREMENTS

DESCRIPTION

UNITS

T1 minimum time from CS falling edge to SCK falling edge.

10ns

T2 minimum time from CS falling edge to SCK rising edge.

80ns

T3 minimum time for the SCK low.

60ns

T4 minimum time for the SCK high.

60ns

T5 minimum time from SCK rise after 8 bits to CS rising edge.

80ns

T6 minimum time from data valid to rising edge of SCK.

60ns

T7 minimum time for data valid after the rising edge of the

SCK.

10ns

T8 minimum time after CS rises until INT/HOLD goes high.

8

µs

B7

B6

B5

B4

B3

B2

B1

B0

DATA IN

SCK

CS

T1

T2

T3

T4

T5

T6

T7

INT/HOLD

T8

FIGURE 6. SPI TIMING

HIP9010