3-435

TABLE 7. Q COEFFICIENT ADDRESSING FOR A 16 TAP INTERPOLATED BY 4 FILTER

IP0

768 =

D0

784 =

D4

800 =

D8

816 =

D12

832

848

864

880

896

912

928

944

960

976

992

1008

IP1

769 =

D1

785 =

D5

801 =

D9

817 =

D13

833

849

865

881

897

913

929

945

961

977

993

1009

IP2

770 =

D2

786 =

D6

D10

818 =

D14

834

850

866

882

898

914

930

946

962

978

994

1010

IP3

771 =

D3

787 =

D7

803 =

D11

819 =

D15

835

851

867

883

899

915

931

947

963

979

995

1011

IP4

772

788

804

820

836

852

868

884

900

916

932

948

964

980

996

1012

IP5

773

789

805

821

837

853

869

885

901

917

933

949

965

981

997

1013

IP6

774

790

806

822

838

854

870

886

902

918

934

950

966

982

998

1014

IP7

775

791

807

823

839

855

871

887

903

919

935

951

967

983

999

1015

IP8

776

792

808

824

840

856

872

888

904

920

936

952

968

984

1000

1016

IP9

777

793

809

825

841

857

873

889

905

921

937

953

969

985

1001

1017

IP10

778

794

810

826

842

858

874

890

906

922

938

954

970

986

1002

1018

IP11

779

795

811

827

843

859

875

891

907

923

939

955

971

987

1003

1019

IP12

780

796

812

828

844

860

876

892

908

924

940

956

972

988

1004

1020

IP13

781

797

813

829

845

861

877

893

909

925

941

957

973

989

1005

1021

IP14

782

798

814

830

846

862

878

894

910

926

942

958

974

990

1006

1022

IP15

783

799

815

831

847

863

879

895

911

927

943

959

975

991

1007

1023

TABLE 8. READ ADDRESS MAP FOR MICRO PROCESSOR INTERFACE

A4

A2

A1

A0

DESCRIPTION

0

X

0

0

Carrier Center Frequency: CF(31:16)

0

X

0

1

Carrier Center Frequency: CF(15:0)

0

X

1

0

Re-Sampler Center Frequency: SF(29:16)

0

X

1

1

Re-Sampler Center Frequency: SF(15:0)

1000

Modulation Control: En Out bit 3; Mod(2:0)

1001

Gain Control: OUTGAIN(7:0)

1010

FIFO Control: FIFO Ready bit 5; I FIFO Empty bit 4; Q FIFO Empty bit 3; RTH(2:0)

1011

Poly-Phase Control: DS(3:0) = b5-2; IP(1:0)

1

1

0

X

EnNCO

1110

Sync Control: Ext Sync Polarity bit 1; Sync Sel bit 0

1111

Test Control

FIFO Ready is the logical inverse of the FIFORDY output. I and Q FIFO empty bits are the output of a “zero” state detector operating on the

address bus for the respective FIFO.

NOTE: See Table 8 for valid Read Addresses.

FIGURE 15. TYPICAL READ SEQUENCE

WR

RD

DON’T CARE

A(9:0)

C(15:0)

HI-Z

READ

HI-Z

READ

READ

READ

HI-Z

HI-Z

HI-Z

1000

1001

1010

1011

HSP50215