ADV7189B_15 datasheet(12/104 Pages) AD

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ADV7189B

Rev. B | Page 12 of 104

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type

Function

3, 9, 14, 31, 71

DGND

Digital Ground.

39, 40, 47, 53,

AGND

Analog Ground.

4, 15

DVDDIO

Digital I/O Supply Voltage (3.3 V).

10, 30, 72

DVDD

Digital Core Supply Voltage (1.8 V).

AVDD

Analog Supply Voltage (3.3 V).

PVDD

PLL Supply Voltage (1.8 V).

42, 44, 46, 58,

60, 62, 41, 43,

45, 57, 59, 61

AIN1toAIN12

Analog Video Input Channels.

INTRQ

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input

video. See the interrupt register map in

132H

Table 86.

13, 16, 25, 63,

65, 69, 70, 77,

No Connect Pins.

35 to32, 24 to

17, 8 to 5,

76 to 73

P0–P19

Video Pixel Output Port.

Horizontal Synchronization Output Signal.

Vertical Synchronization Output Signal.

FIELD

Field Synchronization Output Signal.

SDA

I/O

I2C Port Serial Data Input/Output Pin.

SCLK

I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).

ALSB

This pin selects the I2C address for the ADV7189B. ALSB set to a Logic 0 sets the address for a

write as 0x40; for ALSB set to a logic high, the address selected is 0x42.

RESET

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset

the ADV7189B circuitry.

LLC1

This is a line-locked output clock for the pixel data output by the ADV7189B. Nominally 27 MHz,

but varies up or down according to video line length.

LLC2

This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7189B.

Nominally 13.5 MHz, but varies up or down according to video line length.

XTAL

This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V,

27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

XTAL1

This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external

3.3 V, 27 MHz clock oscillator source is used to clock the ADV7189B. In crystal mode, the crystal

must be a fundamental crystal.

PWRDN

A logic low on this pin places the ADV7189B in a power-down mode. Refer to Power

Management Register in the

133H

I2C Register Maps section for more options on power-down

modes for the ADV7189B.

When set to a logic low, OE enables the pixel output bus, P19 toP0 of the ADV7189B. A logic

high on the OE pin places Pins P19 to P0, HS, VS, SFL into a high impedance state.

ELPF

The recommended external loop filter must be connected to this ELPF pin, as shown in

134H

Figure 46.

SFL

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the

subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video

encoder.

REFOUT

Internal Voltage Reference Output. Refer to

135H

Figure 46 for a recommended capacitor network for

this pin.

CML

The CML pin is a common-mode level for the internal ADCs. Refer to

136H

Figure 46 for a

recommended capacitor network for this pin.

48, 49

CAPY1, CAPY2

ADC’s Capacitor Network. Refer to

137H

Figure 46 for a recommended capacitor network for this pin.

54, 55

CAPC1, CAPC2

ADC’s Capacitor Network. Refer to

138H

Figure 46 for a recommended capacitor network for this pin.

ADV7189B Datasheet(PDF) 12 Page - Analog Devices

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