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UPD16602 Datasheet(PDF) 13 Page - NEC |
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UPD16602 Datasheet(HTML) 13 Page - NEC |
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13 / 16 page ![]() 13 µµµµPD16602 +1.0 –1.5 SWITCHING CHARACTERISTICS (TA = –10 to +75 °°°°C, VDD1 = 3.3 V ±±±±0.3 V, VDD2 =12.5 V, VSS = 0 V) Item Symbol Condition MIN. TYP. MAX. Unit Start pulse output delay tIme tPLH1 CL = 20 pF 12 20 40 ns tPHL2 6.75 11 µs tPHL3 13.5 17 µs tPLH2 6.75 11 µs Driver output delay time tPLH3 CL = 50 pF, R = 50 kΩ 13.5 17 µs Ci1 Logic except for SPR (SPL), TA = 25°C 7 10 pF Ci2 SPR (SPL), TA = 25°C 10 15 pF Input capacitance Ci3 Display signal input pin 20 pF Maximum clock frequency fmax. 20 MHz TIMING REQUIREMENT (TA ==== –10 to +75°C, VDD1 ==== 3.3 V ±±±±0.3 V, VSS ==== 0 V, tr ==== tf ==== 5 ns) Item Symbol Condition MIN. TYP. MAX. Unit Clock pulse width PWCLK Duty = 50 % 25 ns Horizontal synchronous signal pulse width PWHS 300 ns Start pulse setup time tSETUP 10 ns CLK-sampling pulse delay time td1 15 ns Sampling pulse-CLK delay time td2 15 ns Horizontal synchronous signal setup time tHS-SETUP 50 ns Horizontal synchronous signal hold time tHS-HOLD 250 ns HS-start pulse time tHS-SP 1.0 µs Start pulse-HS time tSP-HS 10 ns |
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