Design guidelines for PCB schematic and layout

AN4189

16/23

Doc ID 023809 Rev 1

Consider the ground layout. To avoid interference between power and small signal,

grounding for the different ground planes must be separated as shown below.

Figure 21.

Ground layout

Figure 22.

Thermal layout with large ground, top and bottom layers

The thermal resistance junction-to-ambient (at the bottom of the STA335ML) obtainable with

a ground copper area of 4 x 4 cm and 35 via holes is shown in Figure 23.

Figure 23.

Thermal layout with large ground, thermal and soldering holes

Power ground plane

Channel ground plane

Thermal layout on top layer

Thermal layout on bottom layer

35 via holes

φ: 1.0 mm