ECC logic test

AN4475

22/27

DocID026216 Rev 1

It is important to note that for double word data = 0xFFFF_FFFF_FFFF_FFFF, the correct

ECC check bits should be 0xFF. Therefore, every data vector in the data pattern in Table 1:

Data pattern used by the ECC logic test, except the last one, contains a single-bit ECC error

and results in a single-bit correction.

4.3

UTEST mode ECC logic check

The procedure to use the UTEST mode ECC logic check is listed as below:

1.

Enable UTEST mode (Write 0xF9F9_9999 to UT0 register, UT0[UTE] is set).

2.

Write UT0[SBCE] to 1 (to enable single-bit error correction visibility).

3.

Write UT0[EIE] to 1.

4.

Write UT0[DSI], UT1[DAI] and/or UT2[DAI] bits to provide data and check bit values to

be read. Single or Double bit detections/corrections can be simulated by properly

choosing Data and Check Bit combinations.

5.

Write double word address to receive the data inputted in step 3 into the ADR register.

6.

Reads can now be done through the BIU in a Read Request type fashion. In the event

of a BIU read requested from an address that matches the address in the ADR register,

expected data, and corrections or detections should be observed based on data written

into the UT0[DSI], UT1[DAI] and/or UT2[DAI] registers. MCR[EER] and

MCR[SBCSBC] can be checked to evaluate the status of reads done.

7.

Repeat steps 4 to 6 for all the data vectors in the proposed test data pattern.

8.

Once completed, clear the UT0[EIE] bit to 0.

4.4

Fault coverage and execution time

The described ECC logic test reaches around 90% of fault coverage of ECC decode logic.

The execution of the test code takes about 200

μs at 80 MHz, room temperature and

nominal voltages.