AN2507

Reading and writing to the STCF03 registers through the I2C bus

23/31

7.3

Reading from a single register

The reading operation starts with a START-bit followed by 7 bit device address of STCF03.

The 8-th bit is the R/W bit, which is 0 in this case. STCF03 confirms the receiving of the

address + R/W bit by an acknowledge pulse. The address of the register which should be

read is sent after and confirmed by an acknowledge pulse from STCF03 again. Then the

master generates a START-bit again and sends the device address followed by the R/W-bit,

which is 1 now. STCF03 confirms the receiving of the address + R/W-bit by an acknowledge

pulse, and starts to send data to the master. No acknowledge pulse from the master is

required after receiving the data. Then the master generates a STOP-bit to terminate the

communication. See the Figure 19 below.

Figure 19.

Reading from a single register

7.4

Reading from multiple registers with incremental addressing

Reading from multiple registers starts in the same way as reading from a single register. As

soon as the first register is read, the register address is automatically incremented. If the

master generates an acknowledge pulse after receiving the data from the first register, then

reading from the next register can start immediately without having to send once more the

device and the register addresses. The last acknowledge pulse before the STOP-bit is not

required. See Figure 20 below.

Figure 20.

Reading from multiple registers

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS OF

REGISTER

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA

L

S

B

S

T

O

P

N

O

A

C

SDA LINE

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS OF

REGISTER i

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA i

A

C

K

S

T

O

P

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

N

O

A

C

K

SDA LINE