AN2994 datasheet(14/38 Pages) STMICROELECTRONICS

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Test results and significant waveforms

AN2994

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Doc ID 15796 Rev 2

2.3

Voltage feed-forward

The power stage gain of PFC pre-regulators varies with the square of the RMS input

voltage. So does the crossover frequency (fc) of the overall open-loop gain because the gain

has a single pole characteristic. This leads to large trade-offs in the design. For example,

setting the gain of the error amplifier to get an fc of 20 Hz at 264 Vac means having an fc of

4 Hz at 88 Vac, resulting in sluggish control dynamics. Additionally, the slow control loop

causes large transient current flows during rapid line or load changes that are limited by the

dynamics of the multiplier output. This limit is considered when selecting the sense resistor

to let the full load power pass under minimum line voltage conditions, with some margin. But

a fixed current limit allows excessive power inputs at high lines, whereas a fixed power limit

requires the current limit to vary inversely with the line voltage.

The voltage feed-forward function can compensate for the gain variation with the line voltage

and allow overcoming all of the above-mentioned issues. It consists of deriving a voltage

proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit

(1/V2 corrector) and providing the resulting signal to the multiplier that generates the current

reference for the inner current-control loop. In this way, a change of the line voltage will

cause an inversely proportional change of the half sine amplitude at the output of the

multiplier so that the current reference is adapted to the new operating conditions with

(ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop

gain will be constant throughout the input voltage range, which significantly improves

dynamic behavior at low lines and simplifies loop design.

The L6563S realizes a voltage feed-forward with a technique that makes use of just two

external parts and that limits the feed-forward time constant trade-off issue to only one

direction. A capacitor CFF (C18) and a resistor RFF (R26 + R27), both connected to the VFF

pin (5), complete an internal peak-holding circuit that provides a DC voltage equal to the

peak of the rectified sine wave applied on the MULT pin (pin 3). RFF provides a means of

discharging CFF when the line voltage decreases.

However, a drawback of the VFF technique is an increase in the harmonics; in fact, deriving

a voltage proportional to the RMS line voltage implies a form of integration, which has its

own time constant. If it is too small, the voltage generated will be affected by a considerable

amount of ripple at twice the mains frequency, thus causing a distortion of the current

reference (resulting in high THD and poor PF). If it is too large, there will be a considerable

delay in setting the right amount of feed forward, resulting in excessive overshoot and

undershoot of the pre-regulator's output voltage in response to large line voltage changes.

Clearly, a trade-off is required. For reference, Figure 21 and Figure 22 show a comparison

of the input current shape and the measurement of the THD and 3RD harmonic amplitude

for different CFF values taken from a similar board using the former L6563.

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