AN4504 datasheet(36/41 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

AN4504

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DocID026419 Rev 1

Figure 19. Stream-to-FIFO mode: interrupt latched

Stream-to-FIFO can be used in order to analyze the history of the samples that generated

an interrupt; the standard operation is to read FIFO content when the FIFO mode is

triggered and the FIFO buffer is full and stopped.

6.3.5

Bypass-to-Stream mode

This mode is a combination of the Bypass and Stream modes previously described. In

Bypass-to-Stream mode, the FIFO buffer starts operating in Bypass mode and switches to

Stream mode when the selected interrupt occurs.

Follow these steps for Bypass-to-Stream mode configuration:

Configure desired interrupt generator using register INT1_CFG (0x30).

Turn on FIFO by setting the FIFO_EN bit to “1” in control register 5 (0x24). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are

frozen to the last sample set loaded.

Activate Bypass-to-stream Mode by setting the FM[2:0] field to “100” in the FIFO

control register (0x2E).

The interrupt trigger is related to the IA bit in the INT1_SRC register and it is generated even

if the interrupt signal is not driven to an interrupt pad. Bypass-to-stream mode is sensitive to

the trigger level and not to the trigger edge which means that if Bypass-to-Stream is in

Stream mode and the interrupt condition disappears, the FIFO buffer returns to Bypass

mode because the IA bit becomes zero.

It is recommended to latch the interrupt signal used as the stream trigger in order to avoid

losing interrupt events. If the selected interrupt is latched, register INT1_SRC must be read

to clear the IA bit; after the read, the IA bit takes 2*ODR to go low.

In Stream mode the FIFO buffer continues filling. When the buffer is full, the OVRN bit is set

high and the next samples overwrite the oldest.

AN4504 Datasheet(PDF) 36 Page - STMicroelectronics