AN4504 datasheet(38/41 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

AN4504

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DocID026419 Rev 1

6.5

Retrieving data from FIFO

When FIFO is enabled and the mode is different than Bypass, reading the output registers

(28h to 2Dh) returns the oldest FIFO sample set.

Whenever the output registers are read, their content is moved to the SPI/I2C output buffer.

FIFO slots are ideally shifted up one level in order to release room for a new sample

reception and the output registers load the current oldest value stored in the FIFO buffer.

The whole FIFO content is retrieved by performing thirty two read operations from the

gyroscope output registers, every other read operation returns the same last value until a

new sample set is available in the FIFO buffer.

Data can be retrieved from FIFO using every read byte combination in order to increase the

flexibility of the application (ex: 196 single byte reads, 32 reads of 6 bytes, 1 multiple read of

196 bytes, etc.).

It is recommended to read all FIFO slots in a multiple byte read of 196 bytes (6 output

registers by 32 slots) faster than 1*ODR. In order to minimize communication between the

master and slave, the read address is automatically updated by the device; it rolls back to

0x28 when register 0x2D is reached.

In order to avoid losing data, the right ODR must be selected according to the serial

communication rate available. In the case of standard I2C mode being used (max rate

100 kHz), a single sample set reading takes 830 μs while total FIFO download is about

17.57ms. I2C speed is lower than SPI and it needs about 29 clock pulses to start

communication (start, slave address, device address+write, restart, device address+read)

plus an additional 9 clock pulses for every byte to read. If this recommendation were

followed, the complete FIFO read would be performed faster than 1*ODR which means that

using a standard I2C, the selectable ODR must be lower than 57 Hz. If a fast I2C mode is

used (max rate 400 kHz), the selectable ODR must be lower than 228 Hz.

Figure 22. FIFO read diagram - WTM[4:0] = 10 (hex)

In Figure 22 “Rx” indicates a 6-byte read operation and “F0*” represents a single ODR slot

stretched for the diagram.

AN4504 Datasheet(PDF) 38 Page - STMicroelectronics