Fishbone diagram for Power MOSFET in parallel

AN4250

12/15

DocID024230 Rev 1

5

Fishbone diagram for Power MOSFET in parallel

When the power levels are very high, some PFC makers put in parallel two or more Power

MOSFET devices. In this case, other aspects must be taken in account.

Causes linked to the application

Parasitic inductance

It is generated by interconnection wiring and discrete components. They cause delays and

power losses which affect the balance of the current. It strictly depends on the PCB layout.

Temperature unbalance

A temperature rise causes a decrease of V

th

and an increase of R

DS(on)

.

Decrease of V

th

-> switching loss rise -> thermal runaway.

Increase of R

DS(on)

-> conductive loss rise-> current limitation -> unbalance.

Several factors let two Power MOSFETs work according to different temperatures:

–

Another device is mounted on the same heatsink

–

Different air flow according to the fan

Boost diode

During the turn-on, it impacts on the current spike. If devices with different V

th

are used

(500 mV), a fast diode or a very fast diode involves a different peak current.

Gate circuitry

Decoupling resistor mismatch causes the current unbalance. The device with lower R

gate

leads more current than other one and its temperature, as well as its R

DS(on)

increase.

Causes linked to the material

During the switching phase (turn-on, turn-off), the difference of V

th

leads the device, with its

lower value, to conduct earlier, causing an unbalance of the currents.

The difference of R

DS(on)

causes, during the conduction phase, an unbalance between two

currents. In particular, if one of the two Power MOSFETs has a lower R

DS(on)

, an increase of

its I

D

current is observed, causing an increase of the Power MOSFET temperature.

Gfs influence

Different gfs values, during the commutation, cause substantial differences in relation to the

two currents. This parameter is guaranteed by design and process.