AN2141

Timing diagram

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Timing diagram

The typical timing diagram is shown in Figure 2. The DATA, CLOCK and LATCH waveforms

are shown. The data are changed with the falling edge of the clock frequency. For example,

in Figure 2 one byte (01101001) can be seen. When all data are written to the drivers

through the SPI, the microcontroller sets the latch input terminal (LE) pin to “log 1" and

rewrites the data to the storage registers. In the next step the LE pin is grounded and thus

the following data can be transmitted to the shift registers without changes in the output

stage. The data in the storage registers are converted to the output constant current stages

by the output enable (EO) pin. Thanks to the output enable pin, the brightness can be

regulated through the PWM signal. Both LED array reference designs have adjustable delay

time via potentiometer after implementation of the “latch signal”. Thanks to this feature the

blinking speed can be regulated (time between sending data packets is changed).

Figure 2.

Timing diagram