AN2658

Configuring ADC registers for conversion

Doc ID 14152 Rev 2

13/23

ADC_DBx (if DBUF bit is set) from which they must be retrieved before they are overwritten

by the next set of conversions (especially if continuous mode is also selected).

Register settings:

ADC_CR2: SCAN bit

ADC_CR3: DBUF = 0 or 1 (data buffer registers “not used” or “used”)

Practical use: To collect a set of analog values from different inputs in one shot (for

example to read a sample of several AC voltage waveforms almost simultaneously).

3.2

Conversion speed selection

The total conversion speed of an ADC depends proportionally on the ADC clock frequency,

the sampling time duration and on the ADC resolution. The ADC clock speed must be

selected by selecting the division factor to be applied to the internal master clock. The

sampling time is not customizable and depends on the ADC clock (3 ADC clocks).

Register settings:

ADC_CR1: SPSEL[2:0] bits

3.3

Analog input selection

The device has up to 16 external analog inputs connected to GPIO input pins. Pins to be

used as ADC input function must be configured as floating inputs and the input Schmitt

triggers on these pins should be disabled to avoid unnecessary power consumption. If the

application changes the analog input channel during conversion then the current conversion

is stopped and the next conversion starts on the new channel.

If scan mode is selected then the channel bits define the top channel in the scan sequence

(from channel 1 to the top channel).

Register settings:

ADC_CSR: CH[3:0] bits

3.4

Storing converted values

The converted ADC value is stored in the ADC_DRH and ADC_DRL registers. If buffered

mode is selected then data are stored cyclically in the data buffer registers ADC_DBxRH

and ADC_DBxRL (x= 0..N, N is device dependent, refer to the datasheet).

Because the converted value has a 10 bit length and the data registers have 2x8 bit length,

it is possible to select left or right alignment of the conversion result in the data registers. In

left alignment the 8 most significant bits are stored in a single register, in right alignment the

8 least significant bits are stored in a single register. This can be chosen to suit the

application. Data register reading is buffered - when the first register is read, the second

register is automatically stored in a shadow register to be read later. This prevents reading

data register values from 2 different conversions.

The first register to be read depends on the data alignment. You must read the MSB first in

left alignment mode and read LSB first in right alignment mode.