Configuring ADC registers for conversion

AN2658

14/23

Doc ID 14152 Rev 2

Right alignment has the advantage of fast read access when measuring low level signals. In

cases where the result does not affect the high order bits, you can read only the least

significant byte.

Practical usage: Left alignment is useful for fast read access to the conversion result in 8-

bit resolution.

Register settings:

ADC_CR3: DBUF bit

ADC_CR2: ALIGN bit

ADC_CR3: OVR bit

3.5

Analog watchdog function

The converted ADC sample is compared with the high and low analog watchdog threshold

registers. If the threshold is reached then the AWD flag is set and another status bit in the

analog watchdog status register to indicate the channel on which the event occurred. The

analog watchdog function can be enabled for selected channels only by setting the

corresponding bits in the ADC_AWCRx control registers.

Register settings:

ADC_HTRH, ADC_HTRL, ADC_LTRH, ADC_LTRL - high and low thresholds

ADC_AWCRH, ADC_AWCRL - control registers

ADC_AWSRH, ADC_AWSRL - status registers

ADC_CSR: AWDIE and AWD bits

3.6

ADC interrupt management

ADC interrupt source(s) are selectable from one or more of the following events:

●

End of conversion (EOC) in non buffered mode: generated after each AD conversion

●

End of conversion (EOC) in buffered mode: generated after data buffer registers are full

●

Analog watchdog alert: when converted values reach the high or low threshold values

Event-driven programming can be used for efficiency or for special software requirements.

With this technique, when the main program is running, it is notified of state changes by

events. You can enable the ADC interrupt to give the main program fast asynchronous event

notification at the end of conversion(s). This means the main program does not need to poll

the ADC conversion status flags but only has to process the ADC data results (for example

after storing a set of conversions in a buffer). The reception of the ADC converted data

values is performed by an interrupt routine in the background. In addition, the analog

watchdog interrupt can be used for monitoring a given analog range on the measured

channels.

Register settings:

ADC_CSR: AWDIE, EOCIE bits