AN3117

Performance considerations

Doc ID 16846 Rev 4

11/28

t

S

t

A

t

ACC16

t

RAM16

++

=

where:

●

●

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As a result, the total latency for 16-bit data transfer is 5 system clock cycles.

When the DMA is idle, it compares the priorities of all pending DMA requests (software and

hardware priorities, in this order). The highest priority channel is served and the DMA jumps

to execute the second operation. While a channel is being served (operation 2 or 3

ongoing), no other channel can be served whatever its priority.

As a result, when a DMA transfer is on going, the DMA latency for the highest priority

channel is the sum of the ongoing transfer time (without the arbitration phase) and the

transfer time for the next DMA channel to be served (highest pending priority).

2.2

Data bus bandwidth

When the DMA has priority over the CPU, the maximum data transfer rate is obtained with

16-bit data transfers at 16 MHz. Two bytes are transferred in 5 clock cycles, which makes a

transfer rate of 6.4 Mbytes/s.

For 8-bit data transfers, the maximum rate is 1 byte in 3 clock cycles, that is transfer rate of a

5.3 Mbytes/s.

The data rate is reduced when the CPU takes priority over the DMA for RAM and peripheral

accesses.