AN3117

DMA programming examples

Doc ID 16846 Rev 4

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4.6

DMA channel priority transfer example

In the example below, the priority of the DMA channels changes which has an impact on the

transfers. All transfers are 8 bits in size and have a length of 1.

The DMA channels are configured to perform the following transfers:

●

DMA channel 0: Transfer A: from RAM buffer 2 to TIM3 register

●

DMA channel 1: Transfer B: from RAM buffer 1 to TIM2 register

●

DMA channel 2: Transfer C: from TIM1 register to RAM buffer 1

●

DMA channel 3: Transfer D: from TIM4 register to RAM buffer 2

Before starting any transfer, the RAM buffers and timer registers are initialized as shown in

Table 9.

4.6.1

Transfer example case 1: hardware priority configuration of DMA



channels

In this example, the priority of the channels is maintained at its default configuration: the

hardware priority acts and the software priority stays the same for all channels.

Figure 8.

Example case 1: DMA channel data transfers as a function of time

Table 9.

RAM buffers and timer registers at t = t0

Time

RAM Buffer1

TIM1 ARRL

TIM2 ARRL

TIM3 ARRL

TIM4 ARR

RAM Buffer2

t0

0x00

0x11

0x22

0x33

0x44

0x55

Table 10.

Example case1:

priority configuration of the DMA channels

DMA channel

HW priority

SW priority

Channel 0

Very high

Low

Channel 1

High

Low

Channel 2

Medium

Low

Channel 3

Low

Low

time

t0

t1

t2

t3

t4

ai17423

Hardware priority

Channel 0

Channel 1

Channel 2

Channel 3

Transfer A

Transfer B

Transfer C

Transfer D