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LTC1411

1411f

APPLICATIO S I FOR ATIO

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

AGND1, 2, 3 (Pins 7 to 9), AVM (Pin 11), DGND (Pin 31)

and OGND (Pin 28) and all other analog grounds should

be connected to a single analog ground point. The REFOUT,

REFCOM1, REFCOM2 and AVP should bypass to this

analog ground plane (see Figure 10). No other digital

grounds should be connected to this analog ground

plane. Low impedance analog and digital power supply

common returns are essential to low noise operation of

the ADC and the foil width for these tracks should be as

wide as possible.

Timing and Control

Conversion start is controlled by the CONVST digital input.

The falling edge transition of the CONVST will start a

conversion. Once initiated, it cannot be restarted until the

conversion is complete. Converter status is indicated by

the BUSY output. BUSY is low during a conversion.

The digital output code is updated at the end of conversion

about 7ns after BUSY rises, i.e., output data is not valid on

the rising edge of BUSY. Valid data can be latched with the

falling edge of BUSY or with the rising edge of CONVST. In

either case, the data latched will be for the previous

conversion results. Figures 11a and 11b are the timing

diagrams for the LTC1411.

3V Input/Output Compatible

The LTC1411 operates on a 5V supply, which makes the

device easy to interface to 5V digital systems. This device

can also talk to 3V digital systems: the digital input pins

(CONVST, NAP and SLP) of the LTC1411 recognize 3V or

5V inputs. The LTC1411 has a dedicated output supply pin

(OVDD) that controls the output swings of the digital

output pins (D0 to D13, BUSY and OTR) and allows the

part to talk to either 3V or 5V digital systems. The output

is two’s complement binary.

Figure 12 is the input/output characteristics of the ADC

when AIN– = 2.5V. The code transitions occur midway

between successive integer LSB values (i.e., 0.5LSB,

1.5LSB, 2.5LSB... FS – 1.5LSB). The output code is scaled

such that 1LSB = FS/16384 = 3.6V/16384 = 219.7

µV.

Offset and Full-Scale Adjustment

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figure 13

shows the extra components required for full-scale error

adjustment. Zero offset is achieved by adjusting the

offset applied to the AIN– input. For zero offset error,

apply 2.49989V (i.e., – 0.5LSB) at AIN+ and adjust R2 at

the AIN– input until the output code flickers between 0000

0000 0000 00 and 1111 1111 1111 11. For full-scale

adjustment, an input voltage of 4.29967V (FS – 1.5LSBs)

is applied to AIN+ and R5 is adjusted until the output code

flickers between 0111 1111 1111 10 and 0111 1111

1111 11.

Figure 10. Power Supply Grounding Practice

1411 F10

AIN

REFCOM2

OVDD

DVP

AVP

LTC1411

DIGITAL

SYSTEM

ANALOG

INPUT

CIRCUITRY

REFCOM1

OGND

DGND

AVM

REFIN

REFOUT

AIN

–

AGND1

AGND2

–

AGND3

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