UPD705102 datasheet(46/80 Pages) NEC

46 / 80 page

µPD705102

Data Sheet U13675EJ2V1DS00

Instruction

Operand(s)

Format

Function

SHR

reg1, reg2

Logical right shift. reg2 is logically shifted to

the right by the displacement specified by the

low-order five bits of reg1 (0 is put on the MSB).

The result is written into reg2.

imm5, reg2

Logical right shift. reg2 is logically shifted to

the right by the displacement specified by imm5,

zero-extended to a word. The result is written

into reg2.

SHRD3

reg1, reg2,

VIII

—

Right shift of concatenation. The 64 bits

reg3

consisting of reg3 (high order) and reg2

(low order) are logically shifted to the right by

the displacement specified by the low-order five

bits of reg1. The low-order 32 bits of the result

are written into reg3.

ST.B

reg2,

—

Byte store. disp16, sign-extended to a word,

disp16[reg1]

is added to reg1 to generate an unsigned 32-bit

address. The low-order one byte of data in reg2

is stored at the resulting address.

ST.H

reg2,

—

Halfword store. disp16, sign-extended to a

disp16[reg1]

word, is added to reg1 to generate an unsigned

32-bit address. The low-order two bytes of the

data in reg2 are stored at the resulting address.

Bit 0 of the unsigned 32-bit address is masked

to 0.

ST.W

reg2,

—

Word store. disp16, sign-extended to a word,

disp16[reg1]

is added to reg1 to generate an unsigned 32-bit

address. The word of data in reg2 is stored at

the resulting address. Bits 0 and 1 of the

unsigned 32-bit address are masked to 0.

STBY

—

Processor stop. The processor is placed in

stop mode.

STSR

regID, reg2

—

System register store. The contents of the

system register identified by the system

SUB

reg1, reg2

Subtraction. reg1 is subtracted from reg2.

The difference is written into reg2.

TRAP

vector

—

Software trap. The return PC and PSW are

saved in the system registers:

PSW.EP = 1

→ Save in FEPC, FEPSW

PSW.EP = 0

→ Save in EIPC, EIPSW

The exception code is set in the ECR:

PSW.EP = 1

→ Set in FECC

PSW.EP = 0

→ Set in EICC

PSW flags are set:

PSW.EP = 1

→ Set NP and ID

PSW.EP = 0

→ Set EP and ID

Program execution jumps to the trap handler

address corresponding to the trap vector (0-31)

specified by vector and begins exception

handling.

UPD705102 Datasheet(PDF) 46 Page - NEC

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