UPD705102 datasheet(49/80 Pages) NEC

49 / 80 page

µPD705102

Data Sheet U13675EJ2V1DS00

DC Characteristics (VDDO = 3.0 to 3.6 V, VDDI = 2.3 to 2.7 V)

µPD705102-143 (CPU core frequency

≤ 143 MHz): TA = –40 to +85°C

µPD705102-143 (CPU core frequency

≤ 144 MHz): TA = –40 to +70°C

µPD705102-133:

TA = –40 to +85

°C

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Clock input voltage, low

VKL

Note 1

–0.5

+0.2 VDDO

Clock input voltage, high

VKH

Note 1

0.8 VDDO

VDDO + 0.3

Input voltage, low

VIL

–0.5

+0.6

Input voltage, high

VIH

2.0

VDDO + 0.3

Schmitt input voltage, low

VSL

Note 2

–0.5

+0.2 VDDO

Schmitt input voltage, high

VSH

Note 2

0.8 VDDO

VDDO + 0.3

Output voltage, low

VOL

IOL = 3.2 mA

0.4

Output voltage, high

VOH

IOH = –400

µA

0.85 VDDO

Input leakage current, low

ILIL

VIN = 0 V

–10

µA

Input leakage current, high

ILIH

VIN = VDDO

µA

Output leakage current, low

ILOL

VO = 0 V

–10

µA

Output leakage current, high

ILOH

VO = VDDO

µA

Supply currentNote 3

2.5 V

IDDI

In normal operation Clock division ratio 1/1

115

160

(PLL mode)

Clock division ratio 1/2

Clock division ratio 1/4

In normal operation Clock division ratio 1/1

(Direct mode)

Clock division ratio 1/2

7.5

In HALT mode

In STOP modeNote 4

450

µA

3.3 V

IDDO

In normal operation Clock division ratio 1/1

(PLL mode)

Clock division ratio 1/2

Clock division ratio 1/4

6mA

In normal operation Clock division ratio 1/1

4mA

(Direct mode)

Clock division ratio 1/2

3mA

In HALT mode

In STOP modeNote 4

510

µA

Notes 1. X2 pin, DCK pin, and SCLK pin at external clock input

2. PORT0/SCLK, PORT2/SI, PORT3/RXD

3. Supply current at input clock: 17.85 MHz with output pins open, PLL 8

4. External clock mode when clock input is stopped.

Capacitance

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Input capacitance

fC = 1 MHz

I/O capacitance

CIO

Remark

These parameters are sample values, not the value actually measured.

UPD705102 Datasheet(PDF) 49 Page - NEC

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