UPD72107 datasheet(8/32 Pages) NEC

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µPD72107

SDIP

QFP

QFJ

Active

Pin No.

Level

B/W

L/H

Specifies the data bus that accesses the external

(Byte/Word)

memory when bus master.

B/W = 0

Byte units (8 bits)

B/W = 1

Word units (16 bits)

After power-on, fix the status of the B/W pin.

In the case of word access, the lower data bus is the

contents data of even addresses.

READY

An input signal that is used to extend the MRD and

(Ready)

MWR signal widths output by the

µPD72107 to

adapt to low-speed memory.

When the READY

signal is low level, the MRD and MWR signals

maintain active low. Do not change the READY

signal at any time other than the specified setup/

hold time.

HLDRQ

A hold request signal to the external host processor.

(Hold Request)

When a DMA operation is performed in the

µPD72107,

this signal is activated to switch from bus slave to

bus master.

HLDAK

A hold acknowledge signal from the external host

(Hold Acknowledge)

processor. When the

µPD72107 detects that this

signal is active, the bus slave switches to bus

master, and a DMA operation is started.

AEN

When bus master, this signal enables the latched

(Address Enable)

higher addresses and outputs them to system ad-

dress bus. This signal is also used for disabling

other system bus drivers.

A0, A1

15, 16

30, 31

17, 18

I/O

–

Bidirectional 3-state address lines.

3-state

When bus master (output)

Indicate the lower 2-bit addresses of memory access.

When bus slave (input)

Input addresses when the external host processor

I/O accesses the

µPD72107.

A2 to A15

17 to 30

32 to 47

19 to 32

–

When bus master

(except

3-state

Output bit 2 to bit 15 of memory access addresses.

40, 41)

When bus slave

Become high impedance.

I/O

Pin Name

Function

UPD72107 Datasheet(PDF) 8 Page - NEC

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