UPD72107 datasheet(20/32 Pages) NEC

20 / 32 page

µPD72107

Serial block (2)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

RxC cycle time

tCYR

When on-chip DPLL is used (source clock = RxC)

30.3

When on-chip DPLL is used (source clock = CLK)

125

1000

RxC low-level time

tSSRL

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

RxC high-level time

tSSRH

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

RxC rise time

tSRR

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

RxC fall time

tSRF

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

Transmit/receive data cycle

tCYD

When on-chip DPLL is used (source clock = RxC)

500

When on-chip DPLL is used (source clock = CLK)

2000

16000

TxC low-level time

tTCTCL

When on-chip DPLL is used

0.5tCYD–25

TxC high-level time

tTCTCH

0.5tCYD–25

TxD delay time (vs. TxC

↓)tDTCTD

TxD hold time (vs. TxC

↑)tHTCTD

0.5tCYD–25

Serial clock (when on-chip DPLL is used)

tCYR

tSSRL

tSRF

tTCTCL

tDTCTD

tTCTCH

tHTCTD

tCYD

tSRR

tSSRH

TxC

TxD

RxC

UPD72107 Datasheet(PDF) 20 Page - NEC

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