LTC3453

9

3453fa

APPLICATIO S I FOR ATIO

Input Capacitor Selection

recommended to place at least a 2.2

µF, low ESR bypass

capacitor to ground. See Table 2 for a list of component

suppliers.

Table 2. Capacitor Vendor Information

SUPPLIER

WEB SITE

AVX

www.avxcorp.com

Sanyo

www.sanyovideo.com

Taiyo Yuden

www.t-yuden.com

TDK

www.component.tdk.com

Output Capacitor Selection

The bulk value of the capacitor is set to reduce the ripple

due to charge into the capacitor each cycle. The steady

state ripple due to charge is given by:

%_

•–

•

()

(

)

Ripple Boost

IV

V

OUT MAX

OUT

IN MIN

=

C

CV

f

Ripple Buck

VV

OUT

OUT

IN MAX

OUT

••

%

%_

–•

()

2

1

100

8

2

••

• •

%

()

Vf

L C

IN MAX

OUT

The output capacitance is usually many times larger in

order to handle the transient response of the converter.

For a rule of thumb, the ratio of the operating frequency to

the unity-gain bandwidth of the converter is the amount

the output capacitance will have to increase from the

above calculations in order to maintain the desired tran-

sient response.

The other component of ripple is due to the ESR (equiva-

lent series resistance) of the output capacitor. Low ESR

capacitors should be used to minimize output voltage

ripple. For surface mount applications, Taiyo Yuden, TDK,

AVX ceramic capacitors, AVX TPS series tantalum capaci-

tors or Sanyo POSCAP are recommended. For the white

LED application, a 4.7

µF capacitor value is recommended.

See Table 2 for a list of component suppliers.

Optional Schottky Diodes

Schottky diodes across the synchronous switches B and

D are not required, but provide a lower drop during the

break-before-make time (typically 20ns) of the NMOS to

PMOS transition, improving efficiency. Use a Schottky

diode such as an MBRM120T3 or equivalent. Do not use

ordinary rectifier diodes, since the slow recovery times

will compromise efficiency.

Closing the Feedback Loop

The LTC3453 incorporates voltage mode PWM control.

The control to output gain varies with operation region

(Buck, Boost, Buck/Boost), but is usually no greater than

15. The output filter exhibits a double pole response

given by:

f

LC

Hz

FILTER POLE

OUT

_

••

•

=

π

1

2

The output filter zero is given by:

f

RC

Hz

FILTER ZERO

ESR

OUT

_

••

•

=

π

1

2

A troublesome feature in Boost mode is the right-half

plane zero (RHP), and is given by:

f

V

IL V

Hz

RHPZ

IN

OUT

OUT

=

π

2

2• •

• •

The loop gain is typically rolled off before the RHP zero

frequency.

A simple Type I compensation network can be incorpo-

rated to stabilize the loop but at a cost of reduced band-

width and slower transient response. To ensure proper

phase margin, the loop requires to be crossed over a

decade before the LC double pole.