DocID025810 Rev 3

13/17

AN4434

Data retention

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Where:

–

n is the number of bits in the EEPROM

–

P0 is the probability that 1 cell fails

If one bit fails, the ECC architecture will correct this bit value and therefore P1 is not

significant for the end user as the whole memory can still be read without a single bit error. If

we consider now that a next extrinsic event would lead to one more bit losing its data, this bit

being randomly located over the whole memory array, the probability P2 that this second

falling bit could be located in the same word A is expressed as

–

() 64

⁄

=

Where k is the number of bits of one word (for ECCx4: 4 bytes and 6 ECC bits, this lead to

k=4*8 +6=38).

same word cannot be recovered by ECC logic) for different memory densities.

Note:

If we consider that, during the life of an application:

•

Data written only once (Read only data) are not stressed by further Write cycles, there is

less than the values given in Table 5.

•

Data written several times may be impacted by the SILC effect but, after each Write cycle, the

data are refreshed and therefore the data retention time is “reset”.

Based on these comments, it is wise to consider that the data retention in an application is significantly

better than the worst case values computed in Table 5 and Table 6.

ECCx1 and data retention

CMOS F8H automotive EEPROM devices (1Kb to 16Kb) embed an internal ECCx1 logic

that compares each byte with the 4 additional ECC bits. As a result, if a single bit happens to

be erroneous during a read operation, the ECC detects it and replaces this bit with the

correct value in the read byte. The main benefit of the Error Correction Code is that the ECC

Table 5. ECCx4 memories: probability that one word is not correctly read

Memory capacity

1. ppm: part per million

1 Mbit

0.23

512 Kbit

0.12

256 Kbit

0.06

128 Kbit

0.03

64 Kbit

0.01

32 Kbit

0.01