UPD72871F1 datasheet(29/48 Pages) NEC

29 / 48 page

Preliminary Data Sheet S13925EJ2V0DS00

µµµµPD72870,72871

3.1.21 Offset_60

Cap_ID & Next_Item_Ptr Register

The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the

Next_Item_Ptr describes the location of the next item in the

µPD72870, 72871’s Capability List.

Bits

R/W

Description

7-0

Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI

Power Management registers, while the ID value is assigned by the PCI SIG.

15-8

Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link

List.

3.1.22 Offset_62

Power Management Capabilities Register

This is a 16-bit read-only register that provides information on the power management capabilities of the

µPD72870, 72871.

Bits

R/W

Description

2-0

version Constant value of 001. The power management registers are implemented as defined

in revision 1.0 of PCI Bus Power Management Interface Specification.

PME clock Constant value of 0.

Auxiliary power source Constant value of 0. The alternative power source is not supported.

DIS Constant value of 0.

8,6

Reserved Constant value of 000.

D1_support Constant value of 0. The

µPD72870, 72871 does not support the D1 Power

Management state.

D2_support Constant value of 1. The

µPD72870, 72871 supports the D2 Power Management

state.

15-11

PME_support Constant value of 01100.

UPD72871F1 Datasheet(PDF) 29 Page - NEC