UPD72871F1 datasheet(30/48 Pages) NEC

30 / 48 page

Preliminary Data Sheet S13925EJ2V0DS00

µµµµPD72870,72871

3.1.23 Offset_64

Power Management Control/Status Register

This is a 16-bit read-only register that provides control status information of the

µPD72870, 72871.

Bits

R/W

Description

1,0

R/W

PowerState Default value is undefined. This field is used both to determine the current power

state of the

µPD72870, 72871 and to set the µPD72870, 72871 into a new power state. As D1

is not supported in the current implementation of the

µPD72870, 72871, writing of ‘01’ will be

ignored.

00: D0 (DMA contexts: ON, Link Layer: ON)

01: Reserved (D1 state not supported)

10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon

LinkON being active)

11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon

LinkON being active, Power can be removed)

The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal

signal in the

µPD72870,72871.

7-2

Reserved Constant value of 000000.

8R/W

PME_En Default value of 0. This field is used to enable the specific power management

features of the

µPD72870, 72871.

12-9

Data_Select Constant value of 0000.

14,13

Data_Scale Constant value of 00.

R/W

PME_Status Default value is undefined. A write of ‘1’ clears this bit, while a write of ‘0’ is

ignored.

UPD72871F1 Datasheet(PDF) 30 Page - NEC