UPD75112 datasheet(8/56 Pages) NEC

8 / 56 page

µPD75112(A), 75116(A)

PTH00 to PTH03

TI0

TI1

PTO0

PTO1

SCK

INT4

INT0

INT1

INT2

INT3

PCL

X1, X2

RESET

NC*2

VDD

VSS

3.2 Non-Port Pins

Dual

Function

P20

P21

P01

P02

P03

P00

P10

P11

P12

P13

P22

I/O

Circuit

Type*1

At Reset

Input

Input/Output

Input

Input/output

Input

Input/output

Input

Function

Threshold voltage ariable 4-bit analogy input port.

External event pulse input for the timer/event counter or edge

detect vector interrupt input. 1-bit input enable.

Timer/event counter output.

Serial clock input/output.

Serial data output.

Serial data input.

Edge detect vector interrupt input (for detecting both rising and

falling edges).

Edge detect vector interrupt input (detected edge selectable).

Edge detect testable input (for rising edge detection).

Clock output.

Crystal/ceramic connect pin (system clock oscillation).

In case with the external clock, input a signal to X1 and the

antiphase to X2.

System reset input (low level active).

No Connection

Positive power supply.

GND potential.

*1: Circles indicate Schmitt trigger inputs.

2: When the PWB is shared with the

µPD75P116, connect the NC pin to VDD directly.

UPD75112 Datasheet(PDF) 8 Page - NEC

UPD75112 Datasheet(HTML) 8 Page - NEC

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