UPD75112F datasheet(3/78 Pages) NEC

3 / 78 page

µPD75108F,75112F,75116F

OVERVIEW OF FUNCTIONS

Contents

0.95

µs, 1.91 µs, 15.3 µs (VDD = 4.5 to 5.0 V, 4.19 MHz operation)

µs, 4 µs, 32 µs (VDD = 2.7 to 5.0 V, 2 MHz operation)

3-stage switching capability

0.95

µs (operating at 4.5 to 5.0 V)

1.91

µs (operating at 2.7 V )

8064

× 8 bits (

µPD75108F)

12160

× 8 bits (

µPD75112F)

16256

× 8 bits (

µPD75116F)

512

× 4 bits

4-bits

× 8 × 4 banks (memory mapping)

3 accumulators for different manipulated data lengths

• 1-bit accumulator (CY), 4–bit acculumalor (A), 8-bit accumulator (XA)

Total 58

• CMOS input pins

: 10

• CMOS input/output pins (LED direct drive capability)

: 32

• Middle-high voltage N-ch open-drain input/output pins : 12

(LED direct drive capability, a pull-up resistor can be incorporated bit-wise.)

• Comparator input pins (4-bit precision)

: 4

• 8-bit timer/event counter

× 2

• 8-bit basic interval timer (watchdog timer applicable)

• 2 transfer modes

• Serial transmission/reception modes

• Serial reception mode

• LSB top/MSB top switchable

External : 3 Internal : 4

External : 2

• STOP/HALT mode

• Various bit manipulation instructions (set, reset, test, Boolean operation)

• 8-bit data transfer, comparison, operation, increment/decrement instructions

• 1-byte relative branch instruction

• GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte

• Bit manipulation memory (bit sequential buffer) on chip

• 64-pin plastic QFP (14

× 20 mm)

Item

Basic instructions

Instruction cycle

Minimum instruction

execution time

On-chip memory

General register

Accumulator

Input/output port

Timer/counter

8-bit serial interface

Vector interrupt

Test input

Standby

Instruction set

Others

Package

ROM

RAM

UPD75112F Datasheet(PDF) 3 Page - NEC

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