UPD75112F datasheet(7/78 Pages) NEC

7 / 78 page

PORT 0

PORT 1

P00-P03

P10-P13

PORT 3

PORT 4

PORT 5

PORT 6

PORT 2

P20-P23

P30-P33

P40-P43

P50-P53

P60-P63

PORT 7

P70-P73

SP(8)

BANK

GENERAL REG.

RAM

DATA

MEMORY

512

× 4 BITS

DECODE

AND

CONTROL

ALU

PROGRAM*

COUNTER

RESET

VSS

STAND BY

CONTROL

VDD

CPU CLOCK

CLOCK

GENERATOR

CLOCK

DIVIDER

CLOCK

OUTPUT

CONTROL

PCL/P22

fXX / 2

BASIC

INTERVAL

TIMER

INTER-

RUPT

CONTROL

INTT1

INTBT

PORT 14

P140-P143

PORT 12

P120-P123

TIMER/EVENT

COUNTER

INTT0

TI0

PTO0/P20

TIMER/EVENT

COUNTER

TI1

PTO1/P21

SERIAL

INTERFACE

INTSIO

SCK/P01

SO/P02

SI/P03

PROGRAM-

MABLE

THRESHOLD

PORT #0

PTH00-PTH03

INT4/P00

INT2/P12

INT1/P11

INT0/P10

INT3/P13

PORT 13

P130-P133

PORT 9

P90-P93

PORT 8

P80-P83

BIT SEQ.

BUFFER

(16)

The

µPD75108F program counter is composed of 13 bits and the µPD75112F/75116F program counter is composed of 14 bits

ROM

PROGRAM

MEMORY

8064

× 8 BITS

(

µPD75108F)

12160

× 8 BITS

(

µPD75112F)

16256

× 8 BITS

(

µPD75116F)

UPD75112F Datasheet(PDF) 7 Page - NEC

UPD75112F Datasheet(HTML) 7 Page - NEC

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