UPD75218 datasheet(49/62 Pages) NEC

49 / 62 page

µPD75218

AC CHARACTERISTICS (Ta = –40 to +85

°C , VDD = 2.7 to 6.0 V)

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

VDD = 4.5 to 6.0 V

0.67

2.6

Operation with main

system clock

tCY

CPU clock cycle time

(minimum instruction

execution time = 1

machine cycle)Note 1

Operation with sub-

system clock

114

122

125

VDD = 4.5 to 6.0 V

TI0 input frequency

fTI

0.6

165

VDD = 4.5 to 6.0 V

tTIH,

tTIL

0.83

TI0 input high and low-

level widths

tKCY

SCK cycle time

0.8

0.95

Input

Output

VDD = 4.5 to 6.0 V

3.2

3.8

Input

Output

Input

Output

0.4

tKCY/2–50

VDD = 4.5 to 6.0 V

tKH,

tKL

SCK high and low-level

widths

1.6

tKCY/2–150

Input

Output

100

400

tSIK

SI setup time (referred to

SCK

↑)

µs

MHz

kHz

µs

SI hold time (referred to

SCK

↑)

tKSI

tKSO

Delay from SCK

↓ to SO

output

300

1000

VDD = 4.5 to 6.0 V

Note 2

2tCY

tINTH,

tINTL

Interrupt input high and

low-level widths

tRSL

RESET low-level width

Notes 1.

CPU clock (

Φ) cycle time is determined by the

oscillator frequency of the connected resona-

tor, the system clock control register (SCC)

and the processor clock control register (PCC).

The cycle time tCY characteristics for power

supply voltage VDD when the main system

clock is in operation is shown on the right.

2tCY or 128/fXX is set by interrupt mode register

(IM0) setting.

0.5

Guaranteed operation

range

tCY VS VDD

(Operation with main system clock)

Power supply voltage VDD [V]

INT0

INT1

INT2,

INT4

UPD75218 Datasheet(PDF) 49 Page - NEC

UPD75218 Datasheet(HTML) 49 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL