UPD75516 datasheet(19/70 Pages) NEC

19 / 70 page

µPD75516

6.2

CLOCK GENERATOR

The clock generator operation is determined by the processor clock control register (PCC) and the system clock

control register (SCC).

2 kinds of clocks such as a main system clock and a subsystem clock are available.

In addition, the instruction execution time can be changed.

• 0.95

µs, 1.91 µs, 15.3 µs (Main system clock: 4.19 MHz operation)

• 122

µs (Subsystem clock: 32.768 kHz operation)

Fig. 6–1 Clock Generator Block Diagram

Instruction execution

Remarks

fX = Main system clock frequency

fXT = Subsystem clock frequency

Φ = CPU clock

PCC: Processor clock control register

SCC: System clock control register

One clock cycle (tCY) of

Φ is 1 machine cycle of the instruction. With tCY, refer to "AC CHARACTER-

ISTICS" in 11. "Electrical Specifications".

XT1

XT2

SCC

PCC

HALT*

STOP*

HALT F/F

STOP F/F

1/8~1/4096

SCC3

SCC0

PCC0

PCC1

PCC2

PCC3

• Basic Interval Timer (BT)

• Timer/Event Counter

• Serial Interface

• Watch Timer

• Clock Output Circuit

• A/D Converter

Frequency Divider

Watch Timer

Timer/Pulse

Generator

Subsystem

Clock Oscillation

Circuit

Main System

Clock Oscillation

Circuit

Oscillation

Stop

Frequency Divider

Wait Release

Signal from BT

RESET Signal

Standby Release Signal from

Interrupt Control Circuit

PCC2 and PCC3

Clear

• INT0 Noise Eliminator

• CPU

• Clock Output

Circuit

• INT0 Noise

Eliminator

UPD75516 Datasheet(PDF) 19 Page - NEC

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