LTC1325CSW datasheet(14/24 Pages) LINER

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LTC1325

FUNCTIONAL DESCRIPTIO

–

VDD

4.5V TO 16V

IRF9Z30

IRFZ34

RTRK

1N5818

PGATE

DIS

DISCHARGE

125k

500k

REG

3.072V

16pF

FILTER

LTC1325 • F04

SENSE

BATTERY

RDIS

RSENSE

DR0 TO

DR2

VR1

VR0

DAC VOLTAGE

18mV

34mV

55mV

160mV

0mV

DAC

VR0, VR1

(GAS GAUGE)

CHIP

BOUNDARY

VDAC

DUTY RATIO

GENERATOR

ONE SHOT

111kHz

OSCILLATOR

CHARGE

ADC MUX

Figure 4. Charging Loop Block Diagram

rise as does the voltage across the sense resistor. When

the voltage across the sense resistor is greater than the

output of the integrator, comparator A2 changes state.

This resets the flip-flop and P1 is turned off. Catch diode

D1 clamps the drain of P1 one diode drop below ground

when the inductor flies back and the current through the

inductor starts to drop. The voltage across the sense

resistor also drops and may reach zero and stay there until

the next clock cycle begins.

The average charging current is set by the output of the

DAC (VDAC) and the duty ratio generator. VDAC can be

programmed to one of four values with the following

ratios: 1, 1/3, 1/5 or 1/10. The duty ratio can be set to

1/16, 1/8, 1/4, 1/2 or 1. When the duty ratio is 1, the duty

ratio generator output is always low and the charge loop

operates continuously (see Figure 4). At other duty ratio

settings, the duty generator output is a square wave with

a period of 42 seconds. The time for which the generator

output is low varies with the duty ratio setting. For ex-

ample, if a duty ratio of 1/2 is programmed, the generator

output is low only for 42/2 = 21 seconds. Since the loop

operates for only 21 out of every 42 seconds, the average

charging current is halved. In general, the average charg-

ing current is:

ICHRG = VDAC(Duty Ratio)/RSENSE

Gated PFET Controller

When using an external current regulator or current lim-

ited wall pack, simply remove the inductor L1 and catch

diode D1. Set the DAC control bits VR1 = 1 and VR0 = 1,

and select the desired duty ratio. By insuring that the

voltage at the Sense pin is never greater than 140mV, the

output of the integrator A1 will saturate high and the

comparator A2 will never trip and turn the loop off. This

can be achieved by removing the sense resistor and

grounding the Sense pin or if the gas gauge is to be used,

selecting RSENSE so that RSENSE/ICHRG < 140mV.

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