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LTC1325

APPLICATIONS INFORMATION

PFET to within the maximum gate source voltage rating of

the latter. Finally, D2 clamps VBAT to 15V.

Charging Batteries with Voltages Above 16V

To charge a battery with a maximum (fully charged) voltage

of above 16V, the charging supply VDC must be above 16V.

Thus the charger will need the regulator, level shifter and

clamp mentioned in the previous section. In addition, an

external battery divider must be added to limit the voltage at

the VBAT pin to less than VDD. This is shown in the typical

application circuit, Wide Voltage Battery Charger. The resis-

tors R9 and R10 are selected to divide the battery voltage by

the number of cells in the battery and the battery divider

internal to the LTC1325 is set to divide-by-1. The external

divider prevents VBAT from ever rising to VDD and this causes

the BATP (Battery Present Flag) to be high regardless of

whether the battery is physically present or not. This does not

affect the other operations of the LTC1325.

SOFTWARE DESIGN

A general charging algorithm consists of the following

stages:

Discharge Before Charge

Fast Charge

Top Off Charge

Trickle Charge

Under some operating and storage conditions, NiCd and

NiMH batteries may not provide full capacity. In particular,

repeated shallow charge and discharge cycles cause the

“memory effect” in NiCd batteries. In order to restore full

capacity (battery conditioning), these batteries have to be

subjected to several deep discharge/charge cycles which

will be provided by repetitions of the above algorithm.

Figure 6 shows a simplified flowchart of a charging algo-

rithm. In practice, this flowchart has to be augmented to

take into account the occurrence of fail-safes at any point

in the algorithm. For example, the battery temperature

could rise above HTF during discharging or charging.

General programming notes are as follows:

1. The start bit is always high.

2. The SGL/DIFF bit is generally set to low so that the ADC

makes conversions with respect to ground.

8. REG Pin Loading: The 3.072V regulator has a load

regulation specification of – 5mV/mA. Since the ADC

uses the same regulator as reference, it is desirable to

reduce loading effects on the REG pin especially over

temperature. Thermistors with RTO values of at least

10k at 25

°C are recommended. At 50°C, the ther-

mistor resistance could drop by a factor of 3 from its

value at 25

°C. RL is chosen as explained in the section

on Temperature Sensing. The temperature coefficient

of RL is not critical since the thermistor tempco

dominates the sensing circuit.

9. RDIS: RDIS is selected to limit the discharge current to

a value within the battery discharge specifications and

must have a power rating above IDIS2(RDIS) where:

IDIS = VBAT/[RDIS + RDS(ON)(N1)]

10. PFET(P1) and NFET(N1): For operation of the charge

and discharge loops,

VGS < VDD since the PGATE

and DIS pins swing between 0 and VDD. VGS << VDD

to minimize power dissipation. The power ratings of

P1 and N1 should be above ICHRG

2[RDS(ON)(P1)] and

IDIS

2[RDS(ON)(N1)] respectively. VDS(MAX) should be

above VDD.

Charging from Supplies Above 16V

In many applications, the charging supply is greater than

the 16V maximum VDD ratingoftheLTC1325.TheLTC1325

can easily be adapted to charge the batteries from a

charging supply VDC that is above 16V by adding three

external sub-circuits:

1. A regulator to drop VDC down to within the supply

range of the LTC1325.

2. A level shifter between the PGATE and the gate of the

PFET, P1, to ensure that P1 can be completely turned

off when PGATE rises to VDD.

3. A voltage clamp on the VBAT pin to prevent RTRK from

pulling VBAT above VDD.

The Wide Voltage Battery Charger circuit in the Typical

Application section shows low cost implementations of all

three sub-circuits. C1, R11 and D4 generate a 15V VDD for

the LTC1325. D3, R12 and C2 form a level shifter. The

zener D3 is chosen to clamp the source gate voltage of the

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