UPD75P3036 datasheet(39/64 Pages) NEC

39 / 64 page

µPD75P3036

AC Characteristics (TA = –40 to +85

°C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle timeNote 1

tCY

Operates with

VDD = 2.7 to 5.5 V

0.67

µs

(minimum instruction

main system clock

0.95

µs

execution time = 1

Operates with

114

122

125

µs

machine cycle)

subsystem clock

TI0, TI1, TI2 input frequency

fTI

VDD = 2.7 to 5.5 V

1.0

MHz

275

kHz

TI0, TI1, TI2 high-, low-level

tTIH, tTIL

VDD = 2.7 to 5.5 V

0.48

µs

widths

1.8

µs

Interrupt input high-,

tINTH, tINTL

INT0

IM02 = 0

Note 2

µs

low-level widths

IM02 = 1

µs

INT1, 2, 4

µs

KR0 to KR7

µs

RESET low-level width

tRSL

µs

Notes 1.

The cycle time of the CPU clock (

Φ) is

determined by the oscillation frequency

of the connected resonator (and ex-

ternal clock), the system clock control

control register (PCC).

The figure on the right shows the sup-

ply voltage VDD vs. cycle time tCY char-

acteristics when the device operates

with the main system clock.

2tCY or 128/fX depending on the setting

of the interrupt mode register (IM0).

0.5

(with main system clock)

tCY vs VDD

Operation guaranteed range

Supply voltage VDD [V]

UPD75P3036 Datasheet(PDF) 39 Page - NEC

UPD75P3036 Datasheet(HTML) 39 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL