LTC1629 datasheet(25/28 Pages) LINER

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LTC1629/LTC1629-PG

APPLICATIO S I FOR ATIO

Figure 10. Single and PolyPhase Current Waveforms

ICIN

SW V

ICOUT

ICIN

SW1 V

DUAL PHASE

SINGLE PHASE

SW2 V

ICOUT

RIPPLE

1629 F10

IL1

IL2

Simplified Visual Explanation of How a 2-Phase

Controller Reduces Both Input and Output RMS Ripple

Current

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors. The RMS input ripple current is divided by, and

the effective ripple frequency is multiplied up by the

number of phases used (assuming that the input voltage

is greater than the number of phases used times the output

voltage). The output ripple amplitude is also reduced by,

and the effective ripple frequency is increased by the

number of phases used. Figure 10 graphically illustrates

the principle.

The worst-case RMS ripple current for a single stage

design peaks at twice the value of the output voltage . The

worst-case RMS ripple current for a two stage design

results in peaks at 1/4 and 3/4 of input voltage. When the

RMS current is calculated, higher effective duty factor

results and the peak current levels are divided as long as

the currents in each stage are balanced. Refer to Applica-

tion Note 19 for a detailed description of how to calculate

RMS current for the single stage switching regulator.

Figures 3 and 4 help to illustrate how the input and output

currents are reduced by using an additional phase. The

input current peaks drop in half and the frequency is

doubled for a 2-phase converter. The input capacity re-

quirement is reduced theoretically by a factor of four! A

ceramic input capacitor with its unbeatably low ESR

characteristic can be used.

Figure 4 illustrates the RMS input current drawn from the

input capacitance versus the duty cycle as determined by

the ratio of input and output voltage. The peak input RMS

current level of the single phase system is reduced by 50%

in a 2-phase solution due to the current splitting between

the two stages.

An interesting result of the multi-phase solution is that the

VIN which produces worst-case ripple current for the input

capacitor, VOUT = VIN/2, in the single phase design pro-

duces zero input current ripple in the 2-phase design.

The output ripple current is reduced significantly when

compared to the single phase solution using the same

inductance value because the VOUT/L discharge current

term from the stage(s) that has its bottom MOSFET on

subtracts current from the (VIN - VOUT)/L charging current

resulting from the stage which has its top MOSFET on. The

output ripple current is:

RIPPLE

OUT

−−

()

−+













12 1

where D is duty factor.

The input and output ripple frequency is increased by the

number of stages used, reducing the output capacity

requirements. When VIN is approximately equal to NVOUT

as illustrated in Figures 3 and 4, very low input and output

ripple currents result.

Again, the interesting result of 2-phase operation results

in no output ripple at VOUT = VIN/2. The addition of more

phases by phase locking additional controllers always

results in no net input or output ripple at VOUT/VIN ratios

equal to the number of stages implemented. Designing a

system with a multiple of stages close to the VOUT/VIN ratio

will significantly reduce the ripple voltage at the input and

outputs and thereby improve efficiency, physical size, and

heat generation of the overall switching power supply.

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