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LTC1736 Datasheet(PDF) 23 Page - Linear Technology |
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LTC1736 Datasheet(HTML) 23 Page - Linear Technology |
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23 / 28 page  23 LTC1736 accuracy is ±1%, so the output transient voltage cannot exceed ±0.097V. At VOUT = 1.5V, the maximum output voltage change controlled by the ITH pin would be: ∆= = ± =± V Input Offset V V V V mV OSENSE OUT REF • .• . . 003 1 5 08 56 With optimum resistor values at the ITH pin, the output voltage will swing from 1.55V at minimum load to 1.44V at full load. At this output voltage, active voltage position- ing provides an additional 56mV to the allowable transient voltage on the output capacitors, a 58% improvement over the 97mV allowed without active voltage positioning. The next step is to calculate the ITH pin voltage, VITH, scale factor. The VITH scale factor reflects the ITH pin voltage required for a given load current. VITH controls the peak sense resistor voltage, which represents the DC output current plus one half of the peak-to-peak inductor current. The no load to full load VITH range is from 0.3V to 2.4V, which controls the sense resistor voltage from 0V to the ∆VSENSE(MAX) voltage of 75mV. The calculated VITH scale factor with a 0.003 Ω sense resistor is: V Scale Factor V Range Sense sistor Value V VV V VA ITH ITH SENSE MAX = ∆ == •Re (. – . ) • . . ./ () 24 03 0003 0 075 0 084 VITH at any load current is: VI I V Scale Factor V Offset ITH OUT DC L ITH ITH =+ ∆ + () • 2 At full load current: VA A VA V V ITH MAX PP () •. / . . =+ + = − 15 5 2 0 084 0 3 177 At minimum load current: VA A VA V V ITH MIN PP () .• . / . . =+ + = − 02 2 2 0 084 0 3 040 In this circuit, VITH changes from 0.40V at light load to 1.77V at full load, a 1.37V change. Notice that ∆IL, the peak-to-peak inductor current, changes from light load to full load. Increasing the DC inductor current decreases the permeability of the inductor core material, which de- creases the inductance and increases ∆IL. The amount of inductance change is a function of the inductor design. To create the 30mV input offset, the gain of the error amplifier must be limited. The desired gain is: A V Input Offset V V V ITH = ∆ == 137 20 03 22 8 . (. ) . Connecting a resistor to the output of the transconductance error amplifier will limit the voltage gain. The value of this resistor is: R A Error Amplifier g ms k ITH V m == = 22 8 13 17 54 . . . To center the output voltage variation, VITH must be centered so that no ITH pin current flows when the output voltage is nominal. VITH(NOM) is the average voltage be- tween VITH at maximum output current and minimum output current: V VV V VV VV ITH NOM ITH MAX ITH MIN ITH MIN () () ( ) () – .– . .. =+ =+ = 2 177 0 40 2 0 40 1 085 The Thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor R5 that sources current into the ITH pin and resistor R1 that sinks current to SGND. APPLICATIO S I FOR ATIO |
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