LTC1929C datasheet(4/24 Pages) LINER

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LTC1929

PI FU CTIO S

ELECTRICAL CHARACTERISTICS

Note 3: The LTC1929 is tested in a feedback loop that servos VITH to a

specified voltage and measures the resultant VEAIN.

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 5: When the AMPMD pin is high, the IC pins are connected directly to

the internal op amp inputs. When the AMPMD pin is low, internal MOSFET

switches connect four 40k resistors around the op amp to create a

standard unity-gain differential amp.

Note 1: Absolute Maximum Ratings are those values beyond which the

life of a device may be impaired.

Note 2: TJ is calculated from the ambient temperature TA and power

dissipation PD according to the following formulas:

LTC1929CG: TJ = TA + (PD • 95°C/W)

RUN/SS (Pin 1): Combination of Soft-Start, Run Control

Input and Short-Circuit Detection Timer. A capacitor to

ground at this pin sets the ramp time to full current output.

Forcing this pin below 0.8V causes the IC to shut down all

internal circuitry. All functions are disabled in shutdown.

SENSE1+, SENSE2+ (Pins 2,14): The (+) Input to the

Differential Current Comparators. The ITH pin voltage and

built-in offsets between SENSE– and SENSE+ pins in

conjunction with RSENSE set the current trip threshold.

SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the

Differential Current Comparators.

EAIN (Pin 4): Input to the Error Amplifier that compares

the feedback voltage to the internal 0.8V reference voltage.

This pin is normally connected to a resistive divider from

the output of the differential amplifier (DIFFOUT).

PLLFLTR (Pin 5): The Phase-Locked Loop’s Low Pass

Filter is tied to this pin. Alternatively, this pin can be driven

with an AC or DC voltage source to vary the frequency of

the internal oscillator.

PLLIN (Pin 6): External Synchronization Input to Phase

Detector. This pin is internally terminated to SGND with

50k

Ω. The phase-locked loop will force the rising top gate

signal of controller 1 to be synchronized with the rising

edge of the PLLIN signal.

NC (Pins 7, 28): Not connected.

ITH (Pin 8): Error Amplifier Output and Switching Regula-

tor Compensation Point. Both current comparator’s thresh-

olds increase with this control voltage. The normal voltage

range of this pin is from 0V to 2.4V

SGND (Pin 9): Signal Ground, common to both control-

lers, must be routed separately from the input switched

current ground path to the common (–) terminal(s) of the

COUT capacitor(s).

VDIFFOUT (Pin 10): Output of a Differential Amplifier that

provides true remote output voltage sensing. This pin

normally drives an external resistive divider that sets the

output voltage.

VOS–, VOS+ (Pins 11, 12): Inputs to an Operational Ampli-

fier. Internal precision resistors capable of being elec-

tronically switched in or out can configure it as a differen-

tial amplifier or an uncommitted Op Amp.

AMPMD (Pin 15): This Logic Input pin controls the

connections of internal precision resistors that configure

the operational amplifier as a unity-gain differential ampli-

fier.

TG2, TG1 (Pins 16, 27): High Current Gate Drives for Top

N-Channel MOSFETS. These are the outputs of floating

drivers with a voltage swing equal to INTVCC superim-

posed on the switch node voltage SW.

SW2, SW1 (Pins 17, 26): Switch Node Connections to

Inductors. Voltage swing at these pins is from a Schottky

diode (external) voltage drop below ground to VIN.

BOOST2, BOOST1 (Pins 18, 25): Bootstrapped Supplies

to the Topside Floating Drivers. Capacitors are connected

between the Boost and Switch pins, and Schottky diodes

are tied between the Boost and INTVCC pins.

BG2, BG1 (Pins 19, 23): Voltage Swing High Current Gate

Drives for Bottom Synchronous N-Channel MOSFETS.

Voltage swing at these pins is from ground to INTVCC.

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