RT7306 datasheet(4/17 Pages) RICHTEK

4 / 17 page

RT7306

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS7306-00

July

2015

IL_PK

IQ1_DS

Iin_avg

IDo

Peak Inductor Current

MOSFET Current

Average Input Current

Output Diode Current

VIN

Input Voltage

VQ1_GS

MOSFET Gate Voltage

Figure 2. Inductor Current of CRM with Constant

On-Time Control

RT7306 needs no shunt regulator and opto-coupler at

the secondary side to achieve the output current

regulation. Figure 3 shows several key waveforms of a

conventional flyback converter in Quasi-Resonant (QR)

mode, in which VAUX is the voltage on the auxiliary

winding of the transformer.

VAUX

VIN

IQ1

(VGS)

(VOUT + Vf) x Naux / NS

VIN x Naux / NP

IDOUT

Clamped by Controller

VDS

Figure 3. Key Waveforms of a Flyback Converter

Voltage Clamping Circuit

The RT7306 provides a voltage clamping circuit at ZCD

pin since the voltage on the auxiliary winding is

negative when the main switch is turned on. The lowest

voltage on ZCD pin is clamped near zero to prevent the

IC from being damaged by the negative voltage.

Meanwhile, the sourcing ZCD current (IZCD_SH),

flowing through the upper resistor (RZCD1), is sampled

and held to be a line-voltage-related signal for

propagation delay compensation. The RT7306 embeds

the programmable propagation delay compensation

through CS pin. A sourcing current ICS (equal to

IZCD_SH x KPC) applies a voltage offset (ICS x RPC)

which is proportional to line voltage on CS to

compensate the propagation delay effect. Thus, the

output current can be equal at high and low line

voltage.

Quasi-Resonant Operation

Figure 4 illustrates how valley signal triggers PWM.

no valley signal detected for a long time, the next PWM

is triggered by a starter circuit at end of the interval

(tSTART, 130s typ.) which starts at the rising edge of

the previous PWM signal. A blanking time (tS(MIN),

8.5

μs typ.), which starts at the rising edge of the

previous PWM signal, limits minimum switching period.

When the tS(MIN) interval is on-going, all of valley

signals are not allowed to trigger the next PWM signal.

After the end of the tS(MIN) interval, the coming valley

will trigger the next PWM signal. If one or more valley

signals are detected during the tS(MIN) interval and no

valley is detected after the end of the tS(MIN) interval,

the next PWM signal will be triggered automatically at

end of the tS(MIN) + 5s (typ.).

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