MRF157 datasheet(5/7 Pages) MACOM

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C1 — 1000 pF Ceramic Disc Capacitor

C2, C3, C4 — 0.1

µF Ceramic Disc Capacitor

C5 — 0.01

µF Ceramic Chip Capacitor

C6, C12 — 0.1

µF Ceramic Chip Capacitor

C7, C8 — Two 2200 pF Ceramic Chip Capacitors in Parallel

C7, C8 — Each

C9 — 820 pF Ceramic Chip Capacitor

C10, C11 — 1000 pF Ceramic Chip Capacitor

C13 — 0.47

µF Ceramic Chip Capacitor or Two Smaller

C13 —Values in Parallel

C14 — Unencapsulated Mica, 500 V. Two 1000 pF Units

C14 — in Series, Mounted Under T2

D1 — 1N5357A or Equivalent

D2, D3 — 1N4148 or Equivalent.

IC1 — MC1723 (723) Voltage Regulator

L1, L2 — 15

ηH, Connecting Wires to R14 and R15,

L1, L2 — 2.5 cm Each #20 AWG

Figure 11. 2.0 to 50 MHz, 1.0 kW Wideband Amplifier

L3 — 10

µH, 10 Turns #12 AWG Enameled Wire on

L3 — Fair–Rite Products Corp. Ferrite Toroid #5961000401 or Equivalent

R1, R2 — 1.0K Single Turn Trimpots

R3 — 10K Single Turn Trimpot

R4 — 470 Ohms, 2.0 Watts

R5 — 10 Ohms

R6, R12, R13 — 2.0K Ohms

R7 — 10K Ohms

R8 — Exact Value Depends on Thermistor R9 used

R8 — (Typically 5.0–10K)

R9 — Thermistor, Keystone RL1009–5820–97–D1 or

R9 — Equivalent

R10, R11 — 100 Ohms, 1.0W Carbon

R14, R15 — EMC Technology Model 5308 or KDI

R14, R15 — Pyrofilm PPR 870–150–3 Power Resistors,

R14, R15 — 25 Ohms

T1, T2 — 9:1 and 1:9 Impedance Ratio RF Transformers

Unless otherwise noted, all resistors are 1/2 watt metal film type. All chip capacitors except C13 are ATC type 100/200B or Dielectric Laboratories type C17.

R10

R12

R14

22pF

R15

C14

R11

R13

C13

50 V

OUTPUT

C10

C11

C12

D.U.T

D.U.T.

BIAS 36-50 V

C1 R3

RF POWER MOSFET CONSIDERATIONS

MOSFET CAPACITANCES

The physical structure of a MOSFET results in capacitors

between the terminals. The metal oxide gate structure deter-

mines the capacitors from gate–to–drain (Cgd), and gate–to–

source (Cgs). The PN junction formed during the fabrication

of the TMOS® FET results in a junction capacitance from

drain–to–source (Cds).

These capacitances are characterized as input (Ciss), out-

put (Coss) and reverse transfer (Crss) capacitances on data

sheets. The relationships between the interterminal capaci-

tances and those given on data sheets are shown below. The

Ciss can be specified in two ways:

1. Drain shorted to source and positive voltage at the gate.

2. Positive voltage of the drain in respect to source and zero

volts at the gate. In the latter case the numbers are lower.

However, neither method represents the actual operat-

ing conditions in RF applications.

GATE

DRAIN

SOURCE

Cds

Cgs

Cgd

Ciss = Cgd + Cgs

Coss = Cgd + Cds

Crss = Cgd

LINEARITY AND GAIN CHARACTERISTICS

In addition to the typical IMD and power gain data pres-

ented, Figure 5 may give the designer additional information

on the capabilities of this device. The graph represents the

small signal unity current gain frequency at a given drain cur-

rent level. This is equivalent to fT for bipolar transistors.

Since this test is performed at a fast sweep speed, heating of

the device does not occur. Thus, in normal use, the higher

temperatures may degrade these characteristics to some ex-

tent.

DRAIN CHARACTERISTICS

One figure of merit for a FET is its static resistance in the

full–on condition. This on–resistance, VDS(on), occurs in the

linear region of the output characteristic and is specified un-

der specific test conditions for gate–source voltage and drain

current. For MOSFETs, VDS(on) has a positive temperature

coefficient and constitutes an important design consideration

at high temperatures, because it contributes to the power

dissipation within the device.

GATE CHARACTERISTICS

The gate of the TMOS FET is a polysilicon material, and is

electrically isolated from the source by a layer of oxide. The

input resistance is very high — on the order of 109 ohms —

resulting in a leakage current of a few nanoamperes.

Gate control is achieved by applying a positive voltage

slightly in excess of the gate–to–source threshold voltage,

VGS(th).

REV 1

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