P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM

Page 5

Document # SRAM139 REV OR

Notes:

10. CE and WE must be LOW for WRITE cycle.

11. OE is LOW for this WRITE cycle to show t

12. If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state

13. Write Cycle Time is measured from the last valid address to the first

transitioning address.

AC TEST COnDITIOnS

TRUTH TABLE

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

Mode

CE

WE

I/O

Power

Standby

H

x

High Z

Standby

Read

L

H

D

OUT

Active

Write

L

L

High Z

Active

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

note:

Because of the ultra-high speed of the P4C107, care must be taken when

testing this device; an inadequate setup can cause a normal function-

ing part to be rejected as faulty. Long high-inductance leads that cause

supply bounce must be avoided by bringing the V

directly up to the contactor fingers. A 0.01 µF high frequency capacitor

is also required between V

proper termination must be used; for example, a 50Ω test environment

should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at

the comparator input, and a 116Ω resistor must be used in series with

D