Improved, SPST/SPDT Analog Switches

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7

_____________________________________________________Test Circuits/Timing Diagrams

50%

0V

LOGIC

INPUT

V-

-15V

300

Ω

S

GND

(

)

SWITCH

INPUT

IN

+3V

0V

D

SWITCH

OUTPUT

SWITCH

OUTPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

VL

V+

35pF

+5V

+15V

DG417

DG418

50%

0V

LOGIC

INPUT

V-

-15V

1000

Ω

D

GND

LOGIC

INPUT

S1

IN

+3V

V+

S2

SWITCH

OUTPUT

VL

DG419

+15V

+5V

35pF

Figure 2. DG417/DG418 Switching Time

Figure 3. DG419 Transition Time